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cache: need an isb barrier on icache invalidate

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I don't have a switch but on r-pi4 it's easy to reproduce problems
without this Instruction Synchronization Barrier. Better be safe than
having "fun" dealing with super rare crashes.
This commit is contained in:
notaz 2022-08-02 22:25:54 +03:00
parent 8b17648d0b
commit 79c43a5850
1 changed files with 1 additions and 0 deletions
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nx/source/arm/cache.s
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@ -88,6 +88,7 @@ armICacheInvalidate_L0:
bcc armICacheInvalidate_L0
dsb sy
isb
strb wzr, [x0, #0x104]