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https://github.com/switchbrew/libnx.git
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79c43a5850
I don't have a switch but on r-pi4 it's easy to reproduce problems without this Instruction Synchronization Barrier. Better be safe than having "fun" dealing with super rare crashes.
125 lines
1.6 KiB
ArmAsm
125 lines
1.6 KiB
ArmAsm
.macro CODE_BEGIN name
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.section .text.\name, "ax", %progbits
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.global \name
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.type \name, %function
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.align 2
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.cfi_startproc
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\name:
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.endm
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.macro CODE_END
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.cfi_endproc
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.endm
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CODE_BEGIN armDCacheFlush
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add x1, x1, x0
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mrs x8, CTR_EL0
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lsr x8, x8, #16
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and x8, x8, #0xf
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mov x9, #4
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lsl x9, x9, x8
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sub x10, x9, #1
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bic x8, x0, x10
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mov x10, x1
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mov w1, #1
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mrs x0, tpidrro_el0
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strb w1, [x0, #0x104]
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armDCacheFlush_L0:
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dc civac, x8
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add x8, x8, x9
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cmp x8, x10
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bcc armDCacheFlush_L0
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dsb sy
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strb wzr, [x0, #0x104]
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ret
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CODE_END
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CODE_BEGIN armDCacheClean
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add x1, x1, x0
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mrs x8, CTR_EL0
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lsr x8, x8, #16
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and x8, x8, #0xf
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mov x9, #4
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lsl x9, x9, x8
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sub x10, x9, #1
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bic x8, x0, x10
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mov x10, x1
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mov w1, #1
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mrs x0, tpidrro_el0
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strb w1, [x0, #0x104]
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armDCacheClean_L0:
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dc cvac, x8
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add x8, x8, x9
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cmp x8, x10
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bcc armDCacheClean_L0
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dsb sy
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strb wzr, [x0, #0x104]
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ret
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CODE_END
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CODE_BEGIN armICacheInvalidate
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add x1, x1, x0
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mrs x8, CTR_EL0
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and x8, x8, #0xf
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mov x9, #4
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lsl x9, x9, x8
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sub x10, x9, #1
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bic x8, x0, x10
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mov x10, x1
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mov w1, #1
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mrs x0, tpidrro_el0
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strb w1, [x0, #0x104]
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armICacheInvalidate_L0:
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ic ivau, x8
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add x8, x8, x9
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cmp x8, x10
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bcc armICacheInvalidate_L0
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dsb sy
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isb
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strb wzr, [x0, #0x104]
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ret
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CODE_END
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CODE_BEGIN armDCacheZero
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add x1, x1, x0
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mrs x8, CTR_EL0
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lsr x8, x8, #16
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and x8, x8, #0xf
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mov x9, #4
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lsl x9, x9, x8
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sub x10, x9, #1
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bic x8, x0, x10
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mov x10, x1
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mov w1, #1
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mrs x0, tpidrro_el0
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strb w1, [x0, #0x104]
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armDCacheZero_L0:
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dc zva, x8
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add x8, x8, x9
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cmp x8, x10
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bcc armDCacheZero_L0
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dsb sy
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strb wzr, [x0, #0x104]
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ret
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CODE_END
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