From 79c43a58501e475a3cbf6a61917630aa09a7eab8 Mon Sep 17 00:00:00 2001 From: notaz Date: Tue, 2 Aug 2022 22:25:54 +0300 Subject: [PATCH] cache: need an isb barrier on icache invalidate I don't have a switch but on r-pi4 it's easy to reproduce problems without this Instruction Synchronization Barrier. Better be safe than having "fun" dealing with super rare crashes. --- nx/source/arm/cache.s | 1 + 1 file changed, 1 insertion(+) diff --git a/nx/source/arm/cache.s b/nx/source/arm/cache.s index c5ed394b..ff4da5e0 100644 --- a/nx/source/arm/cache.s +++ b/nx/source/arm/cache.s @@ -88,6 +88,7 @@ armICacheInvalidate_L0: bcc armICacheInvalidate_L0 dsb sy + isb strb wzr, [x0, #0x104]