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Structuring

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This commit is contained in:
plutooo 2018-04-01 04:39:11 +02:00
parent adfe12fc53
commit 165bd8935f
7 changed files with 37 additions and 37 deletions
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2
nx/include/switch/nvidia/cmds/3d.h
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@ -50,5 +50,3 @@ enum {
#define NvReg3D_VertexStreamEnableDivisor(n) \
((NvReg3D_VertexStreamNEnableDivisor) + (n))
void nvCmdsClearColor(NvCmdList* cmds, float colors[4]);

1
nx/include/switch/nvidia/cmds/3d_clear.h Normal file
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@ -0,0 +1 @@
void nvCmdsClearColor(NvCmdList* cmds, float colors[4]);

0
nx/include/switch/nvidia/cmds/3d_init.h Normal file
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4
nx/include/switch/nvidia/cmds/common.h
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@ -1,5 +1,5 @@
void nvCmdsFifoInit(NvCmdList* cmds);
enum {
NvCmdCommon_BindObject = 0
};
void nvCmdsInit(NvCmdList* cmds);

32
nx/source/nvidia/cmds/3d_clear.c Normal file
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@ -0,0 +1,32 @@
#include <switch.h>
#include <string.h>
void nvCmdsClearBuffer(
NvCmdList* cmds, NvBuffer* buf, u32 width, u32 height, float colors[4])
{
NvCmd(cmds, NvIncr(0, NvReg3D_ClearColor,
f2i(colors[0]), f2i(colors[1]), f2i(colors[2]), f2i(colors[3])));
NvCmd(cmds, NvIncr(0, NvReg3D_ScreenScissorHorizontal,
0 | (0x100 << 16), 0 | (0x100 << 16)));
NvCmd(cmds, NvImm(0, NvReg3D_RenderTargetControl, 1)); // bit0 probably enables RT #0
iova_t gpu_addr = nvBufferGetGpuAddr(buf);
NvCmd(cmds,
NvIncr(NvReg3D_RenderTargetNAddr + 0x10*0,
gpu_addr >> 32, gpu_addr,
width, height,
0 /* Format */,
0x1000 /* TileMode */,
1 /* ArrayMode */,
0 /* Stride */,
0 /* BaseLayer */
));
int z;
for (z=0; z<32; z++)
NvCmd(cmds, NvImm(0, NvReg3D_ClearBufferTrigger, 0x3c | (z << 10)));
/*
TODO:
IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0);
IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 0);
*/
}

33
nx/source/nvidia/cmds/3d.c → nx/source/nvidia/cmds/3d_init.c
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@ -1,7 +1,7 @@
#include <switch.h>
#include <string.h>
void nvCmds3DInitialize(NvCmdList* cmds) {
void nvCmdsInit3D(NvCmdList* cmds) {
NvCmd(
cmds,
// ???
@ -99,34 +99,3 @@ void nvCmds3DInitialize(NvCmdList* cmds) {
// TODO: CB_BIND stuff
}
void nvCmdsClearBuffer(
NvCmdList* cmds, NvBuffer* buf, u32 width, u32 height, float colors[4])
{
NvCmd(cmds, NvIncr(0, NvReg3D_ClearColor,
f2i(colors[0]), f2i(colors[1]), f2i(colors[2]), f2i(colors[3])));
NvCmd(cmds, NvIncr(0, NvReg3D_ScreenScissorHorizontal,
0 | (0x100 << 16), 0 | (0x100 << 16)));
NvCmd(cmds, NvImm(0, NvReg3D_RenderTargetControl, 1)); // bit0 probably enables RT #0
iova_t gpu_addr = nvBufferGetGpuAddr(buf);
NvCmd(cmds,
NvIncr(NvReg3D_RenderTargetNAddr + 0x10*0,
gpu_addr >> 32, gpu_addr,
width, height,
0 /* Format */,
0x1000 /* TileMode */,
1 /* ArrayMode */,
0 /* Stride */,
0 /* BaseLayer */
));
int z;
for (z=0; z<32; z++)
NvCmd(cmds, NvImm(0, NvReg3D_ClearBufferTrigger, 0x3c | (z << 10)));
/*
TODO:
IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0);
IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 0);
*/
}

2
nx/source/nvidia/cmds/common.c
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@ -1,7 +1,7 @@
#include <switch.h>
#include <string.h>
void nvCmdsFifoInit(NvCmdList* cmds) {
void nvCmdsInit(NvCmdList* cmds) {
NvCmd(cmds,
NvIncr(0, NvCmdCommon_BindObject, NvClassNumber_3D),
NvIncr(1, NvCmdCommon_BindObject, NvClassNumber_Compute),