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<div id="projectname">libnx<span id="projectnumber"> v4.9.0</span>
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<a href="#pub-attribs">Data Fields</a> </div>
<div class="headertitle"><div class="title">ThreadContext Struct Reference</div></div>
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<p><a class="el" href="structThread.html" title="Thread information structure.">Thread</a> context structure (register dump)
<a href="structThreadContext.html#details">More...</a></p>
<p><code>#include <<a class="el" href="thread__context_8h_source.html">thread_context.h</a>></code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:ad82c03b56b9d81634b661ffe0604d056" id="r_ad82c03b56b9d81634b661ffe0604d056"><td class="memItemLeft" align="right" valign="top"><a id="ad82c03b56b9d81634b661ffe0604d056" name="ad82c03b56b9d81634b661ffe0604d056"></a>
<a class="el" href="unionCpuRegister.html">CpuRegister</a> </td><td class="memItemRight" valign="bottom"><b>cpu_gprs</b> [29]</td></tr>
<tr class="memdesc:ad82c03b56b9d81634b661ffe0604d056"><td class="mdescLeft"> </td><td class="mdescRight">GPRs 0..28. Note: also contains AArch32 SPRs. <br /></td></tr>
<tr class="separator:ad82c03b56b9d81634b661ffe0604d056"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad2c6458d9ddfa3aa760cfb13a096f546" id="r_ad2c6458d9ddfa3aa760cfb13a096f546"><td class="memItemLeft" align="right" valign="top"><a id="ad2c6458d9ddfa3aa760cfb13a096f546" name="ad2c6458d9ddfa3aa760cfb13a096f546"></a>
<a class="el" href="types_8h.html#a3f7e2bcbb0b4c338f3c4f6c937cd4234">u64</a> </td><td class="memItemRight" valign="bottom"><b>fp</b></td></tr>
<tr class="memdesc:ad2c6458d9ddfa3aa760cfb13a096f546"><td class="mdescLeft"> </td><td class="mdescRight">Frame pointer (x29) (AArch64). For AArch32, check r11. <br /></td></tr>
<tr class="separator:ad2c6458d9ddfa3aa760cfb13a096f546"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:afcc39c3f1c13bc0b1fbf626255159204" id="r_afcc39c3f1c13bc0b1fbf626255159204"><td class="memItemLeft" align="right" valign="top"><a id="afcc39c3f1c13bc0b1fbf626255159204" name="afcc39c3f1c13bc0b1fbf626255159204"></a>
<a class="el" href="types_8h.html#a3f7e2bcbb0b4c338f3c4f6c937cd4234">u64</a> </td><td class="memItemRight" valign="bottom"><b>lr</b></td></tr>
<tr class="memdesc:afcc39c3f1c13bc0b1fbf626255159204"><td class="mdescLeft"> </td><td class="mdescRight">Link register (x30) (AArch64). For AArch32, check r14. <br /></td></tr>
<tr class="separator:afcc39c3f1c13bc0b1fbf626255159204"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aef758ef63a99688218a34f83ffa11266" id="r_aef758ef63a99688218a34f83ffa11266"><td class="memItemLeft" align="right" valign="top"><a id="aef758ef63a99688218a34f83ffa11266" name="aef758ef63a99688218a34f83ffa11266"></a>
<a class="el" href="types_8h.html#a3f7e2bcbb0b4c338f3c4f6c937cd4234">u64</a> </td><td class="memItemRight" valign="bottom"><b>sp</b></td></tr>
<tr class="memdesc:aef758ef63a99688218a34f83ffa11266"><td class="mdescLeft"> </td><td class="mdescRight">Stack pointer (AArch64). For AArch32, check r13. <br /></td></tr>
<tr class="separator:aef758ef63a99688218a34f83ffa11266"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a96595fe9fc720501f214e67efdb33510" id="r_a96595fe9fc720501f214e67efdb33510"><td class="memItemLeft" align="right" valign="top"><a id="a96595fe9fc720501f214e67efdb33510" name="a96595fe9fc720501f214e67efdb33510"></a>
<a class="el" href="unionCpuRegister.html">CpuRegister</a> </td><td class="memItemRight" valign="bottom"><b>pc</b></td></tr>
<tr class="memdesc:a96595fe9fc720501f214e67efdb33510"><td class="mdescLeft"> </td><td class="mdescRight">Program counter. <br /></td></tr>
<tr class="separator:a96595fe9fc720501f214e67efdb33510"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a57268e9f35a3e8a23fc1d572314bfb0a" id="r_a57268e9f35a3e8a23fc1d572314bfb0a"><td class="memItemLeft" align="right" valign="top"><a id="a57268e9f35a3e8a23fc1d572314bfb0a" name="a57268e9f35a3e8a23fc1d572314bfb0a"></a>
<a class="el" href="types_8h.html#afaa62991928fb9fb18ff0db62a040aba">u32</a> </td><td class="memItemRight" valign="bottom"><b>psr</b></td></tr>
<tr class="memdesc:a57268e9f35a3e8a23fc1d572314bfb0a"><td class="mdescLeft"> </td><td class="mdescRight">PSTATE or cpsr. <br /></td></tr>
<tr class="separator:a57268e9f35a3e8a23fc1d572314bfb0a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0058cef147b3a3fa39ddfd5a2aab251d" id="r_a0058cef147b3a3fa39ddfd5a2aab251d"><td class="memItemLeft" align="right" valign="top"><a id="a0058cef147b3a3fa39ddfd5a2aab251d" name="a0058cef147b3a3fa39ddfd5a2aab251d"></a>
<a class="el" href="unionFpuRegister.html">FpuRegister</a> </td><td class="memItemRight" valign="bottom"><b>fpu_gprs</b> [32]</td></tr>
<tr class="memdesc:a0058cef147b3a3fa39ddfd5a2aab251d"><td class="mdescLeft"> </td><td class="mdescRight">32 general-purpose NEON registers. <br /></td></tr>
<tr class="separator:a0058cef147b3a3fa39ddfd5a2aab251d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3be3464ab2a24d792d47912421725e3e" id="r_a3be3464ab2a24d792d47912421725e3e"><td class="memItemLeft" align="right" valign="top"><a id="a3be3464ab2a24d792d47912421725e3e" name="a3be3464ab2a24d792d47912421725e3e"></a>
<a class="el" href="types_8h.html#afaa62991928fb9fb18ff0db62a040aba">u32</a> </td><td class="memItemRight" valign="bottom"><b>fpcr</b></td></tr>
<tr class="memdesc:a3be3464ab2a24d792d47912421725e3e"><td class="mdescLeft"> </td><td class="mdescRight">Floating-point control register. <br /></td></tr>
<tr class="separator:a3be3464ab2a24d792d47912421725e3e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a997bc7507afe8bcdec7004ddd5c13490" id="r_a997bc7507afe8bcdec7004ddd5c13490"><td class="memItemLeft" align="right" valign="top"><a id="a997bc7507afe8bcdec7004ddd5c13490" name="a997bc7507afe8bcdec7004ddd5c13490"></a>
<a class="el" href="types_8h.html#afaa62991928fb9fb18ff0db62a040aba">u32</a> </td><td class="memItemRight" valign="bottom"><b>fpsr</b></td></tr>
<tr class="memdesc:a997bc7507afe8bcdec7004ddd5c13490"><td class="mdescLeft"> </td><td class="mdescRight">Floating-point status register. <br /></td></tr>
<tr class="separator:a997bc7507afe8bcdec7004ddd5c13490"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aad8e88aca367ff4562f2f4bed3c18d2d" id="r_aad8e88aca367ff4562f2f4bed3c18d2d"><td class="memItemLeft" align="right" valign="top"><a id="aad8e88aca367ff4562f2f4bed3c18d2d" name="aad8e88aca367ff4562f2f4bed3c18d2d"></a>
<a class="el" href="types_8h.html#a3f7e2bcbb0b4c338f3c4f6c937cd4234">u64</a> </td><td class="memItemRight" valign="bottom"><b>tpidr</b></td></tr>
<tr class="memdesc:aad8e88aca367ff4562f2f4bed3c18d2d"><td class="mdescLeft"> </td><td class="mdescRight">EL0 Read/Write Software <a class="el" href="structThread.html" title="Thread information structure.">Thread</a> ID Register. <br /></td></tr>
<tr class="separator:aad8e88aca367ff4562f2f4bed3c18d2d"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p><a class="el" href="structThread.html" title="Thread information structure.">Thread</a> context structure (register dump) </p>
</div><hr/>The documentation for this struct was generated from the following file:<ul>
<li>include/switch/arm/<a class="el" href="thread__context_8h_source.html">thread_context.h</a></li>
</ul>
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