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Const correctness in nvGpuZbcAddColor (and fix comment typo)

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fincs 2019-05-17 21:20:11 +02:00
parent 320b054f6e
commit d966bee9fa
2 changed files with 3 additions and 3 deletions
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2
nx/include/switch/nvidia/gpu.h
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@ -11,5 +11,5 @@ const nvioctl_zcull_info* nvGpuGetZcullInfo(void);
const u32* nvGpuGetTpcMasks(u32 *num_masks_out); const u32* nvGpuGetTpcMasks(u32 *num_masks_out);
Result nvGpuZbcGetActiveSlotMask(u32 *out_slot, u32 *out_mask); Result nvGpuZbcGetActiveSlotMask(u32 *out_slot, u32 *out_mask);
Result nvGpuZbcAddColor(u32 color_l2[4], u32 color_ds[4], u32 format); Result nvGpuZbcAddColor(const u32 color_l2[4], const u32 color_ds[4], u32 format);
Result nvGpuZbcAddDepth(float depth); Result nvGpuZbcAddDepth(float depth);

4
nx/source/nvidia/gpu.c
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@ -7,7 +7,7 @@
#include "nvidia/ioctl.h" #include "nvidia/ioctl.h"
#include "nvidia/gpu.h" #include "nvidia/gpu.h"
// Official software hardcodes this for both Tegra X1 (and even K1). // Official software hardcodes this for Tegra X1 (and even K1).
#define NUM_TPC_MASKS 1 #define NUM_TPC_MASKS 1
static u32 g_ctrlgpu_fd = -1; static u32 g_ctrlgpu_fd = -1;
@ -90,7 +90,7 @@ Result nvGpuZbcGetActiveSlotMask(u32 *out_slot, u32 *out_mask)
return rc; return rc;
} }
Result nvGpuZbcAddColor(u32 color_l2[4], u32 color_ds[4], u32 format) Result nvGpuZbcAddColor(const u32 color_l2[4], const u32 color_ds[4], u32 format)
{ {
return nvioctlNvhostCtrlGpu_ZbcSetTable(g_ctrlgpu_fd, color_ds, color_l2, 0, format, NVGPU_ZBC_TYPE_COLOR); return nvioctlNvhostCtrlGpu_ZbcSetTable(g_ctrlgpu_fd, color_ds, color_l2, 0, format, NVGPU_ZBC_TYPE_COLOR);
} }