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Fixes for vnClear

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This commit is contained in:
plutooo 2018-04-14 02:06:34 +02:00
parent 34a35bab27
commit b10f0c2b72
4 changed files with 57 additions and 40 deletions
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6
nx/include/switch/nvidia/cmds/vn.h
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@ -4,8 +4,12 @@ typedef struct {
NvBuffer vertex_runout; NvBuffer vertex_runout;
NvBuffer const_buffer0; NvBuffer const_buffer0;
NvBuffer const_buffer1;
} Vn; } Vn;
#define VnCmd(vn, ...) \ #define VnCmd(vn, ...) \
NvCmd(&(vn)->cmd_list, __VA_ARGS__) NvCmd(&(vn)->cmd_list, __VA_ARGS__)
static inline Result vnSubmit(Vn* v) {
NvFence f;
return nvGpfifoSubmit(&v->parent->gpfifo, &v->cmd_list, &f);
}

34
nx/source/nvidia/cmds/3d_clear.c
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@ -1,32 +1,32 @@
#include <switch.h> #include <switch.h>
#include <string.h> #include <string.h>
void nvVnClearBuffer( void vnClearBuffer(
Vn* vn, NvBuffer* buf, u32 width, u32 height, float colors[4]) Vn* vn, NvBuffer* buf, u32 width, u32 height, float colors[4])
{ {
VnCmd(vn, NvIncr(0, NvReg3D_ClearColor, VnCmd(vn,
f2i(colors[0]), f2i(colors[1]), f2i(colors[2]), f2i(colors[3]))); NvIncr(0, NvReg3D_ClearColor, f2i(colors[0]), f2i(colors[1]), f2i(colors[2]), f2i(colors[3])),
VnCmd(vn, NvIncr(0, NvReg3D_ScreenScissorHorizontal, NvIncr(0, NvReg3D_ScreenScissorHorizontal, 0 | (width << 16), 0 | (height << 16)),
0 | (0x100 << 16), 0 | (0x100 << 16))); NvIncr(0, NvReg3D_RenderTargetControl, (076543210 << 4) | 1)); // bit0 probably enables RT #0
VnCmd(vn, NvImm(0, NvReg3D_RenderTargetControl, 1)); // bit0 probably enables RT #0
// TODO: this function does not seem to update buffer, but when i give it an invalid gpu_addr i get a gpfifo error so at least something is going on
iova_t gpu_addr = nvBufferGetGpuAddr(buf); iova_t gpu_addr = nvBufferGetGpuAddr(buf);
VnCmd(vn, VnCmd(vn,
NvIncr(NvReg3D_RenderTargetNAddr + 0x10*0, NvIncr(0, NvReg3D_RenderTargetNAddr + 0x10*0,
gpu_addr >> 32, gpu_addr, gpu_addr >> 32, gpu_addr,
width, height, width, height,
0 /* Format */, 0xc2, /* Format */
0x1000 /* TileMode */, 0x1000, /* TileMode */
1 /* ArrayMode */, 1, /* ArrayMode */
0 /* Stride */, 0, /* Stride */
0 /* BaseLayer */ 0 /* BaseLayer */
)); ));
// Disable zeta + multisample
VnCmd(vn, NvImm(0, 0x54E, 0), NvImm(0, 0x54D, 0));
// Only layer 0.
int z; int z;
for (z=0; z<32; z++) for (z=0; z<1; z++)
VnCmd(vn, NvImm(0, NvReg3D_ClearBufferTrigger, 0x3c | (z << 10))); VnCmd(vn, NvImm(0, NvReg3D_ClearBufferTrigger, 0x3c | (z << 10)));
/*
TODO:
IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0);
IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 0);
*/
} }

42
nx/source/nvidia/cmds/3d_init.c
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@ -71,9 +71,10 @@ Result vnInit3D(Vn* vn) {
NvIncr(0, NvReg3D_Layer, 0x10000), NvIncr(0, NvReg3D_Layer, 0x10000),
NvImm(0, 0x488, 5), NvImm(0, 0x488, 5),
NvIncr(0, 0x514, 0x00800008), NvIncr(0, 0x514, 0x00800008),
NvImm(0, 0xab, 3), //NvImm(0, 0xab, 3), // FAULTY
NvImm(0, 0xa4, 0), //NvImm(0, 0xa4, 0),
NvImm(0, 0x221, 0x3f)); //NvImm(0, 0x221, 0x3f));
);
// TODO: Call macro_14f(0x00418800, 1, 1). // TODO: Call macro_14f(0x00418800, 1, 1).
// TODO: Call macro_14f(0x00419a08, 0, 0x10). // TODO: Call macro_14f(0x00419a08, 0, 0x10).
@ -96,7 +97,7 @@ Result vnInit3D(Vn* vn) {
// TODO: Of what size is this buffer actually supposed to be? // TODO: Of what size is this buffer actually supposed to be?
rc = nvBufferCreateRw( rc = nvBufferCreateRw(
&vn->vertex_runout, 0x10000/*???*/, 0x1000, 0, &vn->parent->addr_space); &vn->vertex_runout, 0x10000, 0x1000, 0, &vn->parent->addr_space);
if (R_FAILED(rc)) if (R_FAILED(rc))
return rc; return rc;
@ -109,8 +110,8 @@ Result vnInit3D(Vn* vn) {
// TODO: Write an addr(?) to low->0x8e4,high->0x8e5 // TODO: Write an addr(?) to low->0x8e4,high->0x8e5
// TODO: Write 0 to 0x8e6, 0x8e7. // TODO: Write 0 to 0x8e6, 0x8e7.
// TODO: Call macro_226(5 /* addr_hi */, 0x00056900 /* addr_low */, 0x100) // TODO: Call macro_226(5, 0x00056900, 0x100)
// TODO: Call macro_226(5 /* addr_hi */, 0x00056A00 /* addr_low */, 0x800) // TODO: Call macro_226(5, 0x00056A00, 0x800)
// Bind all const buffers index 0 to same buffer (of size 0x5f00). // Bind all const buffers index 0 to same buffer (of size 0x5f00).
rc = nvBufferCreateRw( rc = nvBufferCreateRw(
@ -139,8 +140,8 @@ Result vnInit3D(Vn* vn) {
VnCmd(vn, VnCmd(vn,
NvIncr(0, NvIncr(0,
NvReg3D_ConstantBufferSize, NvReg3D_ConstantBufferSize,
0x5f00, /* Size */ 0x5f00, // Size
gpu_addr >> 32, gpu_addr /* Addr */ gpu_addr >> 32, gpu_addr // Addr
), ),
NvImm(0, NvReg3D_ConstantBufferBind(i), 0x21), NvImm(0, NvReg3D_ConstantBufferBind(i), 0x21),
NvIncrOnce( NvIncrOnce(
@ -158,6 +159,8 @@ Result vnInit3D(Vn* vn) {
NvIncr(0, NvReg3D_ViewportControl, 0x181d) // ??? NvIncr(0, NvReg3D_ViewportControl, 0x181d) // ???
); );
// NO issue.
// Reset all the viewports. // Reset all the viewports.
for (i=0; i<16; i++) { for (i=0; i<16; i++) {
VnCmd(vn, VnCmd(vn,
@ -176,7 +179,7 @@ Result vnInit3D(Vn* vn) {
); );
} }
VnCmd(vn, NvImm(0, NvReg3D_ScreenHorizontalControl, 0x10)); //VnCmd(vn, NvImm(0, NvReg3D_ScreenHorizontalControl, 0x10)); // FAULTY
// Reset all the scissors. // Reset all the scissors.
for (i=0; i<16; i++) { for (i=0; i<16; i++) {
@ -215,7 +218,8 @@ Result vnInit3D(Vn* vn) {
NvImm(0, NvReg3D_MmeShadowScratch(0x33), 0x200) NvImm(0, NvReg3D_MmeShadowScratch(0x33), 0x200)
); );
VnCmd(vn, VnCmd(
vn,
NvIncr(0, NvReg3D_SampleCountEnable, 1), NvIncr(0, NvReg3D_SampleCountEnable, 1),
NvIncr(0, NvReg3D_ClipDistanceEnable, 0xff), NvIncr(0, NvReg3D_ClipDistanceEnable, 0xff),
NvIncr(0, NvReg3D_MsaaMask, 0xffff, 0xffff, 0xffff, 0xffff), NvIncr(0, NvReg3D_MsaaMask, 0xffff, 0xffff, 0xffff, 0xffff),
@ -224,30 +228,31 @@ Result vnInit3D(Vn* vn) {
NvImm(0, NvReg3D_PointCoordReplace, 4), NvImm(0, NvReg3D_PointCoordReplace, 4),
NvImm(0, NvReg3D_VpPointSize, 1), NvImm(0, NvReg3D_VpPointSize, 1),
NvImm(0, 0x68b, 0), NvImm(0, 0x68b, 0),
NvImm(0, NvReg3D_StencilTwoSideEnable, 1), NvImm(0, NvReg3D_StencilTwoSideEnable, 1));
NvImm(0, 0xe2a, 0x184) // NvImm(0, 0xe2a, 0x184)); // MACRO CALL NOT IMPLEMENTED
);
// TODO: Call macro_206(0x184); // TODO: Call macro_206(0x184);
VnCmd(vn, NvIncr(0, NvReg3D_ConstantBufferLoadN, 0x44fffe00)); //VnCmd(vn, NvIncr(0, NvReg3D_ConstantBufferLoadN, 0x44fffe00));
VnCmd(vn, VnCmd(
vn,
NvImm(0, NvReg3D_ZetaArrayMode, 1), NvImm(0, NvReg3D_ZetaArrayMode, 1),
NvImm(0, NvReg3D_ConservativeRaster, 0), NvImm(0, NvReg3D_ConservativeRaster, 0),
); );
// TODO: Call macro_14f(0x00418800, 0, 0x01800000); // TODO: Call macro_14f(0x00418800, 0, 0x01800000);
VnCmd(vn, VnCmd(
vn,
NvImm(0, NvReg3D_MmeShadowScratch(0x34), 0), NvImm(0, NvReg3D_MmeShadowScratch(0x34), 0),
NvImm(0, 0xbb, 0), NvImm(0, 0xbb, 0),
NvImm(0, NvReg3D_MultisampleRasterEnable, 0), NvImm(0, NvReg3D_MultisampleRasterEnable, 0),
NvImm(0, NvReg3D_CoverageModulationEnable, 0), NvImm(0, NvReg3D_CoverageModulationEnable, 0),
NvImm(0, 0x44c, 0x13), NvImm(0, 0x44c, 0x13), // not in fermi ?
NvImm(0, NvReg3D_MultisampleCoverageToColor, 0) NvImm(0, NvReg3D_MultisampleCoverageToColor, 0)
); );
VnCmd(vn, NvIncr(0, NvReg3D_CodeAddr, 4, 0x00000000)); //VnCmd(vn, NvIncr(0, NvReg3D_CodeAddr, 4, 0x00000000));
VnCmd(vn, VnCmd(vn,
NvImm(0, NvReg3D_MmeShadowScratch(0x27), 0x230), NvImm(0, NvReg3D_MmeShadowScratch(0x27), 0x230),
@ -319,6 +324,5 @@ Result vnInit3D(Vn* vn) {
NvIncr(0, 0x1e9, 0x7ff8), NvIncr(0, 0x1e9, 0x7ff8),
NvIncr(0, 0x1ea, 0x7ffc) NvIncr(0, 0x1ea, 0x7ffc)
); );
return 0; return 0;
} }

11
nx/source/nvidia/cmds/common.c
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@ -1,14 +1,23 @@
#include <switch.h> #include <switch.h>
#include <string.h> #include <string.h>
void vnCmdsInit(Vn* vn, NvGpu* parent) Result vnInit(Vn* vn, NvGpu* parent)
{ {
Result rc;
vn->parent = parent; vn->parent = parent;
rc = nvCmdListCreate(&vn->cmd_list, parent, 0x1000*4);
if (R_FAILED(rc))
return rc;
VnCmd(vn, VnCmd(vn,
NvIncr(0, NvCmdCommon_BindObject, NvClassNumber_3D), NvIncr(0, NvCmdCommon_BindObject, NvClassNumber_3D),
NvIncr(1, NvCmdCommon_BindObject, NvClassNumber_Compute), NvIncr(1, NvCmdCommon_BindObject, NvClassNumber_Compute),
NvIncr(2, NvCmdCommon_BindObject, NvClassNumber_Kepler), NvIncr(2, NvCmdCommon_BindObject, NvClassNumber_Kepler),
NvIncr(3, NvCmdCommon_BindObject, NvClassNumber_2D), NvIncr(3, NvCmdCommon_BindObject, NvClassNumber_2D),
NvIncr(4, NvCmdCommon_BindObject, NvClassNumber_DMA)); NvIncr(4, NvCmdCommon_BindObject, NvClassNumber_DMA));
return rc;
} }