From b10f0c2b7200b97c0d6483c9b4cf30c76e9dea57 Mon Sep 17 00:00:00 2001 From: plutooo Date: Sat, 14 Apr 2018 02:06:34 +0200 Subject: [PATCH] Fixes for vnClear --- nx/include/switch/nvidia/cmds/vn.h | 6 +++- nx/source/nvidia/cmds/3d_clear.c | 36 ++++++++++++------------ nx/source/nvidia/cmds/3d_init.c | 44 ++++++++++++++++-------------- nx/source/nvidia/cmds/common.c | 11 +++++++- 4 files changed, 57 insertions(+), 40 deletions(-) diff --git a/nx/include/switch/nvidia/cmds/vn.h b/nx/include/switch/nvidia/cmds/vn.h index f67cd732..905cb470 100644 --- a/nx/include/switch/nvidia/cmds/vn.h +++ b/nx/include/switch/nvidia/cmds/vn.h @@ -4,8 +4,12 @@ typedef struct { NvBuffer vertex_runout; NvBuffer const_buffer0; - NvBuffer const_buffer1; } Vn; #define VnCmd(vn, ...) \ NvCmd(&(vn)->cmd_list, __VA_ARGS__) + +static inline Result vnSubmit(Vn* v) { + NvFence f; + return nvGpfifoSubmit(&v->parent->gpfifo, &v->cmd_list, &f); +} diff --git a/nx/source/nvidia/cmds/3d_clear.c b/nx/source/nvidia/cmds/3d_clear.c index 5545f679..3f608447 100644 --- a/nx/source/nvidia/cmds/3d_clear.c +++ b/nx/source/nvidia/cmds/3d_clear.c @@ -1,32 +1,32 @@ #include #include -void nvVnClearBuffer( +void vnClearBuffer( Vn* vn, NvBuffer* buf, u32 width, u32 height, float colors[4]) { - VnCmd(vn, NvIncr(0, NvReg3D_ClearColor, - f2i(colors[0]), f2i(colors[1]), f2i(colors[2]), f2i(colors[3]))); - VnCmd(vn, NvIncr(0, NvReg3D_ScreenScissorHorizontal, - 0 | (0x100 << 16), 0 | (0x100 << 16))); - VnCmd(vn, NvImm(0, NvReg3D_RenderTargetControl, 1)); // bit0 probably enables RT #0 + VnCmd(vn, + NvIncr(0, NvReg3D_ClearColor, f2i(colors[0]), f2i(colors[1]), f2i(colors[2]), f2i(colors[3])), + NvIncr(0, NvReg3D_ScreenScissorHorizontal, 0 | (width << 16), 0 | (height << 16)), + NvIncr(0, NvReg3D_RenderTargetControl, (076543210 << 4) | 1)); // bit0 probably enables RT #0 + // TODO: this function does not seem to update buffer, but when i give it an invalid gpu_addr i get a gpfifo error so at least something is going on iova_t gpu_addr = nvBufferGetGpuAddr(buf); VnCmd(vn, - NvIncr(NvReg3D_RenderTargetNAddr + 0x10*0, + NvIncr(0, NvReg3D_RenderTargetNAddr + 0x10*0, gpu_addr >> 32, gpu_addr, width, height, - 0 /* Format */, - 0x1000 /* TileMode */, - 1 /* ArrayMode */, - 0 /* Stride */, - 0 /* BaseLayer */ + 0xc2, /* Format */ + 0x1000, /* TileMode */ + 1, /* ArrayMode */ + 0, /* Stride */ + 0 /* BaseLayer */ )); + + // Disable zeta + multisample + VnCmd(vn, NvImm(0, 0x54E, 0), NvImm(0, 0x54D, 0)); + + // Only layer 0. int z; - for (z=0; z<32; z++) + for (z=0; z<1; z++) VnCmd(vn, NvImm(0, NvReg3D_ClearBufferTrigger, 0x3c | (z << 10))); - /* - TODO: - IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0); - IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 0); - */ } diff --git a/nx/source/nvidia/cmds/3d_init.c b/nx/source/nvidia/cmds/3d_init.c index 6d2ffcef..236f6c11 100644 --- a/nx/source/nvidia/cmds/3d_init.c +++ b/nx/source/nvidia/cmds/3d_init.c @@ -71,9 +71,10 @@ Result vnInit3D(Vn* vn) { NvIncr(0, NvReg3D_Layer, 0x10000), NvImm(0, 0x488, 5), NvIncr(0, 0x514, 0x00800008), - NvImm(0, 0xab, 3), - NvImm(0, 0xa4, 0), - NvImm(0, 0x221, 0x3f)); + //NvImm(0, 0xab, 3), // FAULTY + //NvImm(0, 0xa4, 0), + //NvImm(0, 0x221, 0x3f)); + ); // TODO: Call macro_14f(0x00418800, 1, 1). // TODO: Call macro_14f(0x00419a08, 0, 0x10). @@ -96,7 +97,7 @@ Result vnInit3D(Vn* vn) { // TODO: Of what size is this buffer actually supposed to be? rc = nvBufferCreateRw( - &vn->vertex_runout, 0x10000/*???*/, 0x1000, 0, &vn->parent->addr_space); + &vn->vertex_runout, 0x10000, 0x1000, 0, &vn->parent->addr_space); if (R_FAILED(rc)) return rc; @@ -109,8 +110,8 @@ Result vnInit3D(Vn* vn) { // TODO: Write an addr(?) to low->0x8e4,high->0x8e5 // TODO: Write 0 to 0x8e6, 0x8e7. - // TODO: Call macro_226(5 /* addr_hi */, 0x00056900 /* addr_low */, 0x100) - // TODO: Call macro_226(5 /* addr_hi */, 0x00056A00 /* addr_low */, 0x800) + // TODO: Call macro_226(5, 0x00056900, 0x100) + // TODO: Call macro_226(5, 0x00056A00, 0x800) // Bind all const buffers index 0 to same buffer (of size 0x5f00). rc = nvBufferCreateRw( @@ -139,8 +140,8 @@ Result vnInit3D(Vn* vn) { VnCmd(vn, NvIncr(0, NvReg3D_ConstantBufferSize, - 0x5f00, /* Size */ - gpu_addr >> 32, gpu_addr /* Addr */ + 0x5f00, // Size + gpu_addr >> 32, gpu_addr // Addr ), NvImm(0, NvReg3D_ConstantBufferBind(i), 0x21), NvIncrOnce( @@ -158,6 +159,8 @@ Result vnInit3D(Vn* vn) { NvIncr(0, NvReg3D_ViewportControl, 0x181d) // ??? ); + // NO issue. + // Reset all the viewports. for (i=0; i<16; i++) { VnCmd(vn, @@ -176,7 +179,7 @@ Result vnInit3D(Vn* vn) { ); } - VnCmd(vn, NvImm(0, NvReg3D_ScreenHorizontalControl, 0x10)); + //VnCmd(vn, NvImm(0, NvReg3D_ScreenHorizontalControl, 0x10)); // FAULTY // Reset all the scissors. for (i=0; i<16; i++) { @@ -215,7 +218,8 @@ Result vnInit3D(Vn* vn) { NvImm(0, NvReg3D_MmeShadowScratch(0x33), 0x200) ); - VnCmd(vn, + VnCmd( + vn, NvIncr(0, NvReg3D_SampleCountEnable, 1), NvIncr(0, NvReg3D_ClipDistanceEnable, 0xff), NvIncr(0, NvReg3D_MsaaMask, 0xffff, 0xffff, 0xffff, 0xffff), @@ -224,30 +228,31 @@ Result vnInit3D(Vn* vn) { NvImm(0, NvReg3D_PointCoordReplace, 4), NvImm(0, NvReg3D_VpPointSize, 1), NvImm(0, 0x68b, 0), - NvImm(0, NvReg3D_StencilTwoSideEnable, 1), - NvImm(0, 0xe2a, 0x184) - ); + NvImm(0, NvReg3D_StencilTwoSideEnable, 1)); + // NvImm(0, 0xe2a, 0x184)); // MACRO CALL NOT IMPLEMENTED // TODO: Call macro_206(0x184); - VnCmd(vn, NvIncr(0, NvReg3D_ConstantBufferLoadN, 0x44fffe00)); + //VnCmd(vn, NvIncr(0, NvReg3D_ConstantBufferLoadN, 0x44fffe00)); - VnCmd(vn, + VnCmd( + vn, NvImm(0, NvReg3D_ZetaArrayMode, 1), NvImm(0, NvReg3D_ConservativeRaster, 0), - ); + ); // TODO: Call macro_14f(0x00418800, 0, 0x01800000); - VnCmd(vn, + VnCmd( + vn, NvImm(0, NvReg3D_MmeShadowScratch(0x34), 0), NvImm(0, 0xbb, 0), NvImm(0, NvReg3D_MultisampleRasterEnable, 0), NvImm(0, NvReg3D_CoverageModulationEnable, 0), - NvImm(0, 0x44c, 0x13), + NvImm(0, 0x44c, 0x13), // not in fermi ? NvImm(0, NvReg3D_MultisampleCoverageToColor, 0) ); - VnCmd(vn, NvIncr(0, NvReg3D_CodeAddr, 4, 0x00000000)); + //VnCmd(vn, NvIncr(0, NvReg3D_CodeAddr, 4, 0x00000000)); VnCmd(vn, NvImm(0, NvReg3D_MmeShadowScratch(0x27), 0x230), @@ -319,6 +324,5 @@ Result vnInit3D(Vn* vn) { NvIncr(0, 0x1e9, 0x7ff8), NvIncr(0, 0x1ea, 0x7ffc) ); - return 0; } diff --git a/nx/source/nvidia/cmds/common.c b/nx/source/nvidia/cmds/common.c index ad6cc6e3..122577ae 100644 --- a/nx/source/nvidia/cmds/common.c +++ b/nx/source/nvidia/cmds/common.c @@ -1,14 +1,23 @@ #include #include -void vnCmdsInit(Vn* vn, NvGpu* parent) +Result vnInit(Vn* vn, NvGpu* parent) { + Result rc; + vn->parent = parent; + rc = nvCmdListCreate(&vn->cmd_list, parent, 0x1000*4); + + if (R_FAILED(rc)) + return rc; + VnCmd(vn, NvIncr(0, NvCmdCommon_BindObject, NvClassNumber_3D), NvIncr(1, NvCmdCommon_BindObject, NvClassNumber_Compute), NvIncr(2, NvCmdCommon_BindObject, NvClassNumber_Kepler), NvIncr(3, NvCmdCommon_BindObject, NvClassNumber_2D), NvIncr(4, NvCmdCommon_BindObject, NvClassNumber_DMA)); + + return rc; }