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Started on nvidia/cmds/*

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This commit is contained in:
plutooo 2018-03-25 18:56:59 +02:00
parent 66e3810ef8
commit 8fc8d42d61
7 changed files with 26 additions and 7 deletions
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2
nx/Makefile
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@ -24,7 +24,7 @@ VERSION := $(LIBNX_MAJOR).$(LIBNX_MINOR).$(LIBNX_PATCH)
#---------------------------------------------------------------------------------
TARGET := nx
#BUILD := build
SOURCES := source/arm source/kernel source/services source/display source/nvidia source/nvidia/gpu source/nvidia/ioctl source/runtime source/runtime/devices source/runtime/util/utf
SOURCES := source/arm source/kernel source/services source/display source/nvidia source/nvidia/gpu source/nvidia/ioctl source/nvidia/cmds/ source/runtime source/runtime/devices source/runtime/util/utf
DATA := data
INCLUDES := include external/bsd/include

1
nx/include/switch.h
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@ -68,6 +68,7 @@ extern "C" {
#include "switch/nvidia/gpu/3d_ctx.h"
#include "switch/nvidia/gpu/error_notifier.h"
#include "switch/nvidia/gpu/gpu.h"
#include "switch/nvidia/cmds/common.h"
#include "switch/runtime/env.h"

3
nx/include/switch/nvidia/cmds/3d.h Normal file
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@ -0,0 +1,3 @@
enum {
NvReg3D_MultisampleEnable = 0x54d
};

5
nx/include/switch/nvidia/cmds/common.h Normal file
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@ -0,0 +1,5 @@
void nvCmdsFifoInit(NvCmdList* cmds);
enum {
NvCmdCommon_BindObject = 0
};

10
nx/include/switch/nvidia/gpu/cmd_list.h
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@ -9,10 +9,8 @@ typedef struct {
Result nvCmdListCreate(NvCmdList* c, NvGpu* parent, size_t max_cmds);
void nvCmdListClose(NvCmdList* c);
iova_t nvCmdListGetGpuAddr(NvCmdList* c);
u64 nvCmdListGetListSize(NvCmdList* c);
u32* nvCmdListInsert(NvCmdList* c, size_t num_cmds);
#define NvCmd(cmd_list, ...) do { \
@ -20,14 +18,14 @@ u32* nvCmdListInsert(NvCmdList* c, size_t num_cmds);
memcpy(nvCmdListInsert(cmd_list, sizeof(_)/4), _, sizeof(_)); \
} while (0)
#define NvImm(reg, subc, val) \
#define NvImm(subc, reg, val) \
(0x80000000 | (reg) | ((subc) << 13) | ((val) << 16))
#define NvRep(reg, subc, ...) \
#define NvRep(subc, reg, ...) \
(0x60000000 | ((reg) | ((subc) << 13) | ((sizeof((u32[]) { __VA_ARGS__ })) << 16))), __VA_ARGS__
#define NvIncr(reg, subc, ...) \
#define NvIncr(subc, reg, ...) \
(0x20000000 | ((reg) | ((subc) << 13) | ((sizeof((u32[]) { __VA_ARGS__ })) << 16))), __VA_ARGS__
#define NvIncrOnce(reg, subc, ...) \
#define NvIncrOnce(subc, reg, ...) \
(0xA0000000 | ((reg) | ((subc) << 13) | ((sizeof((u32[]) { __VA_ARGS__ })) << 16))), __VA_ARGS__

2
nx/source/nvidia/cmds/3d.c Normal file
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@ -0,0 +1,2 @@
#include <switch.h>

10
nx/source/nvidia/cmds/common.c Normal file
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@ -0,0 +1,10 @@
#include <switch.h>
#include <string.h>
void nvCmdsFifoInit(NvCmdList* cmds) {
NvCmd(cmds, NvIncr(0, NvCmdCommon_BindObject, NvClassNumber_3D));
NvCmd(cmds, NvIncr(1, NvCmdCommon_BindObject, NvClassNumber_Compute));
NvCmd(cmds, NvIncr(2, NvCmdCommon_BindObject, NvClassNumber_Kepler));
NvCmd(cmds, NvIncr(3, NvCmdCommon_BindObject, NvClassNumber_2D));
NvCmd(cmds, NvIncr(4, NvCmdCommon_BindObject, NvClassNumber_DMA));
}