mirror of
https://github.com/switchbrew/libnx.git
synced 2025-06-21 20:42:44 +02:00
Introduce nvidia/types.h & move NvBufferKind to it (renamed to NvKind)
This commit is contained in:
fincs
parent
27f5aecea8
commit
30e2ca8ec3
@ -1,4 +1,5 @@
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#pragma once
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#include "types.h"
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typedef struct NvAddressSpace {
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u32 fd;
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@ -17,7 +18,7 @@ Result nvAddressSpaceReserveAlign(NvAddressSpace* a, NvPageSize align, u32 pages
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Result nvAddressSpaceReserveAtFixedAddr(NvAddressSpace* a, iova_t addr, u32 pages, NvPageSize page_sz);
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Result nvAddressSpaceReserveFull(NvAddressSpace* a);
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Result nvAddressSpaceMapBuffer(NvAddressSpace* a, u32 fd, NvBufferKind kind, iova_t* iova_out);
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Result nvAddressSpaceMapBuffer(NvAddressSpace* a, u32 fd, NvKind kind, iova_t* iova_out);
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struct NvChannel;
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Result nvAddressSpaceBindToChannel(NvAddressSpace* a, struct NvChannel* channel);
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@ -1,248 +1,12 @@
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#pragma once
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#include "../types.h"
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#include "types.h"
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#include "address_space.h"
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typedef enum {
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NvBufferFlags_Writable=1,
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NvBufferFlags_Nintendo=0x20000,
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} NvBufferFlags;
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typedef enum {
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NvBufferKind_Pitch=0x0,
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NvBufferKind_Z16=0x1,
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NvBufferKind_Z16_2C=0x2,
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NvBufferKind_Z16_MS2_2C=0x3,
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NvBufferKind_Z16_MS4_2C=0x4,
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NvBufferKind_Z16_MS8_2C=0x5,
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NvBufferKind_Z16_MS16_2C=0x6,
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NvBufferKind_Z16_2Z=0x7,
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NvBufferKind_Z16_MS2_2Z=0x8,
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NvBufferKind_Z16_MS4_2Z=0x9,
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NvBufferKind_Z16_MS8_2Z=0xa,
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NvBufferKind_Z16_MS16_2Z=0xb,
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NvBufferKind_Z16_4CZ=0xc,
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NvBufferKind_Z16_MS2_4CZ=0xd,
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NvBufferKind_Z16_MS4_4CZ=0xe,
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NvBufferKind_Z16_MS8_4CZ=0xf,
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NvBufferKind_Z16_MS16_4CZ=0x10,
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NvBufferKind_S8Z24=0x11,
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NvBufferKind_S8Z24_1Z=0x12,
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NvBufferKind_S8Z24_MS2_1Z=0x13,
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NvBufferKind_S8Z24_MS4_1Z=0x14,
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NvBufferKind_S8Z24_MS8_1Z=0x15,
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NvBufferKind_S8Z24_MS16_1Z=0x16,
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NvBufferKind_S8Z24_2CZ=0x17,
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NvBufferKind_S8Z24_MS2_2CZ=0x18,
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NvBufferKind_S8Z24_MS4_2CZ=0x19,
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NvBufferKind_S8Z24_MS8_2CZ=0x1a,
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NvBufferKind_S8Z24_MS16_2CZ=0x1b,
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NvBufferKind_S8Z24_2CS=0x1C,
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NvBufferKind_S8Z24_MS2_2CS=0x1d,
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NvBufferKind_S8Z24_MS4_2CS=0x1e,
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NvBufferKind_S8Z24_MS8_2CS=0x1f,
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NvBufferKind_S8Z24_MS16_2CS=0x20,
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NvBufferKind_S8Z24_4CSZV=0x21,
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NvBufferKind_S8Z24_MS2_4CSZV=0x22,
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NvBufferKind_S8Z24_MS4_4CSZV=0x23,
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NvBufferKind_S8Z24_MS8_4CSZV=0x24,
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NvBufferKind_S8Z24_MS16_4CSZV=0x25,
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NvBufferKind_V8Z24_MS4_VC12=0x26,
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NvBufferKind_V8Z24_MS4_VC4=0x27,
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NvBufferKind_V8Z24_MS8_VC8=0x28,
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NvBufferKind_V8Z24_MS8_VC24=0x29,
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NvBufferKind_S8=0x2a,
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NvBufferKind_S8_2S=0x2b,
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NvBufferKind_V8Z24_MS4_VC12_1ZV=0x2e,
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NvBufferKind_V8Z24_MS4_VC4_1ZV=0x2f,
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NvBufferKind_V8Z24_MS8_VC8_1ZV=0x30,
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NvBufferKind_V8Z24_MS8_VC24_1ZV=0x31,
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NvBufferKind_V8Z24_MS4_VC12_2CS=0x32,
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NvBufferKind_V8Z24_MS4_VC4_2CS=0x33,
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NvBufferKind_V8Z24_MS8_VC8_2CS=0x34,
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NvBufferKind_V8Z24_MS8_VC24_2CS=0x35,
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NvBufferKind_V8Z24_MS4_VC12_2CZV=0x3a,
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NvBufferKind_V8Z24_MS4_VC4_2CZV=0x3b,
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NvBufferKind_V8Z24_MS8_VC8_2CZV=0x3c,
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NvBufferKind_V8Z24_MS8_VC24_2CZV=0x3d,
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NvBufferKind_V8Z24_MS4_VC12_2ZV=0x3e,
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NvBufferKind_V8Z24_MS4_VC4_2ZV=0x3f,
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NvBufferKind_V8Z24_MS8_VC8_2ZV=0x40,
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NvBufferKind_V8Z24_MS8_VC24_2ZV=0x41,
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NvBufferKind_V8Z24_MS4_VC12_4CSZV=0x42,
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NvBufferKind_V8Z24_MS4_VC4_4CSZV=0x43,
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NvBufferKind_V8Z24_MS8_VC8_4CSZV=0x44,
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NvBufferKind_V8Z24_MS8_VC24_4CSZV=0x45,
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NvBufferKind_Z24S8=0x46,
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NvBufferKind_Z24S8_1Z=0x47,
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NvBufferKind_Z24S8_MS2_1Z=0x48,
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NvBufferKind_Z24S8_MS4_1Z=0x49,
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NvBufferKind_Z24S8_MS8_1Z=0x4a,
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NvBufferKind_Z24S8_MS16_1Z=0x4b,
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NvBufferKind_Z24S8_2CS=0x4c,
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NvBufferKind_Z24S8_MS2_2CS=0x4d,
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NvBufferKind_Z24S8_MS4_2CS=0x4e,
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NvBufferKind_Z24S8_MS8_2CS=0x4f,
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NvBufferKind_Z24S8_MS16_2CS=0x50,
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NvBufferKind_Z24S8_2CZ=0x51,
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NvBufferKind_Z24S8_MS2_2CZ=0x52,
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NvBufferKind_Z24S8_MS4_2CZ=0x53,
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NvBufferKind_Z24S8_MS8_2CZ=0x54,
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NvBufferKind_Z24S8_MS16_2CZ=0x55,
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NvBufferKind_Z24S8_4CSZV=0x56,
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NvBufferKind_Z24S8_MS2_4CSZV=0x57,
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NvBufferKind_Z24S8_MS4_4CSZV=0x58,
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NvBufferKind_Z24S8_MS8_4CSZV=0x59,
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NvBufferKind_Z24S8_MS16_4CSZV=0x5a,
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NvBufferKind_Z24V8_MS4_VC12=0x5b,
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NvBufferKind_Z24V8_MS4_VC4=0x5C,
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NvBufferKind_Z24V8_MS8_VC8=0x5d,
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NvBufferKind_Z24V8_MS8_VC24=0x5e,
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NvBufferKind_Z24V8_MS4_VC12_1ZV=0x63,
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NvBufferKind_Z24V8_MS4_VC4_1ZV=0x64,
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NvBufferKind_Z24V8_MS8_VC8_1ZV=0x65,
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NvBufferKind_Z24V8_MS8_VC24_1ZV=0x66,
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NvBufferKind_Z24V8_MS4_VC12_2CS=0x67,
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NvBufferKind_Z24V8_MS4_VC4_2CS=0x68,
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NvBufferKind_Z24V8_MS8_VC8_2CS=0x69,
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NvBufferKind_Z24V8_MS8_VC24_2CS=0x6a,
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NvBufferKind_Z24V8_MS4_VC12_2CZV=0x6f,
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NvBufferKind_Z24V8_MS4_VC4_2CZV=0x70,
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NvBufferKind_Z24V8_MS8_VC8_2CZV=0x71,
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NvBufferKind_Z24V8_MS8_VC24_2CZV=0x72,
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NvBufferKind_Z24V8_MS4_VC12_2ZV=0x73,
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NvBufferKind_Z24V8_MS4_VC4_2ZV=0x74,
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NvBufferKind_Z24V8_MS8_VC8_2ZV=0x75,
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NvBufferKind_Z24V8_MS8_VC24_2ZV=0x76,
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NvBufferKind_Z24V8_MS4_VC12_4CSZV=0x77,
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NvBufferKind_Z24V8_MS4_VC4_4CSZV=0x78,
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NvBufferKind_Z24V8_MS8_VC8_4CSZV=0x79,
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NvBufferKind_Z24V8_MS8_VC24_4CSZV=0x7a,
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NvBufferKind_ZF32=0x7b,
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NvBufferKind_ZF32_1Z=0x7C,
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NvBufferKind_ZF32_MS2_1Z=0x7d,
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NvBufferKind_ZF32_MS4_1Z=0x7e,
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NvBufferKind_ZF32_MS8_1Z=0x7f,
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NvBufferKind_ZF32_MS16_1Z=0x80,
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NvBufferKind_ZF32_2CS=0x81,
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NvBufferKind_ZF32_MS2_2CS=0x82,
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NvBufferKind_ZF32_MS4_2CS=0x83,
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NvBufferKind_ZF32_MS8_2CS=0x84,
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NvBufferKind_ZF32_MS16_2CS=0x85,
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NvBufferKind_ZF32_2CZ=0x86,
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NvBufferKind_ZF32_MS2_2CZ=0x87,
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NvBufferKind_ZF32_MS4_2CZ=0x88,
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NvBufferKind_ZF32_MS8_2CZ=0x89,
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NvBufferKind_ZF32_MS16_2CZ=0x8a,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC12=0x8b,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC4=0x8c,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC8=0x8d,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC24=0x8e,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC12_1CS=0x8f,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC4_1CS=0x90,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC8_1CS=0x91,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC24_1CS=0x92,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC12_1ZV=0x97,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC4_1ZV=0x98,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC8_1ZV=0x99,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC24_1ZV=0x9a,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC12_1CZV=0x9b,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC4_1CZV=0x9c,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC8_1CZV=0x9d,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC24_1CZV=0x9e,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC12_2CS=0x9f,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC4_2CS=0xa0,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC8_2CS=0xa1,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC24_2CS=0xa2,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC12_2CSZV=0xa3,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC4_2CSZV=0xa4,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC8_2CSZV=0xa5,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC24_2CSZV=0xa6,
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NvBufferKind_ZF32_X16V8S8_MS4_VC12=0xa7,
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NvBufferKind_ZF32_X16V8S8_MS4_VC4=0xa8,
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NvBufferKind_ZF32_X16V8S8_MS8_VC8=0xa9,
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NvBufferKind_ZF32_X16V8S8_MS8_VC24=0xaa,
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NvBufferKind_ZF32_X16V8S8_MS4_VC12_1CS=0xab,
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NvBufferKind_ZF32_X16V8S8_MS4_VC4_1CS=0xac,
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NvBufferKind_ZF32_X16V8S8_MS8_VC8_1CS=0xad,
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NvBufferKind_ZF32_X16V8S8_MS8_VC24_1CS=0xae,
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NvBufferKind_ZF32_X16V8S8_MS4_VC12_1ZV=0xb3,
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NvBufferKind_ZF32_X16V8S8_MS4_VC4_1ZV=0xb4,
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NvBufferKind_ZF32_X16V8S8_MS8_VC8_1ZV=0xb5,
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NvBufferKind_ZF32_X16V8S8_MS8_VC24_1ZV=0xb6,
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NvBufferKind_ZF32_X16V8S8_MS4_VC12_1CZV=0xb7,
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NvBufferKind_ZF32_X16V8S8_MS4_VC4_1CZV=0xb8,
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NvBufferKind_ZF32_X16V8S8_MS8_VC8_1CZV=0xb9,
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NvBufferKind_ZF32_X16V8S8_MS8_VC24_1CZV=0xba,
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NvBufferKind_ZF32_X16V8S8_MS4_VC12_2CS=0xbb,
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NvBufferKind_ZF32_X16V8S8_MS4_VC4_2CS=0xbc,
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NvBufferKind_ZF32_X16V8S8_MS8_VC8_2CS=0xbd,
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NvBufferKind_ZF32_X16V8S8_MS8_VC24_2CS=0xbe,
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NvBufferKind_ZF32_X16V8S8_MS4_VC12_2CSZV=0xbf,
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NvBufferKind_ZF32_X16V8S8_MS4_VC4_2CSZV=0xc0,
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NvBufferKind_ZF32_X16V8S8_MS8_VC8_2CSZV=0xc1,
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NvBufferKind_ZF32_X16V8S8_MS8_VC24_2CSZV=0xc2,
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NvBufferKind_ZF32_X24S8=0xc3,
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NvBufferKind_ZF32_X24S8_1CS=0xc4,
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NvBufferKind_ZF32_X24S8_MS2_1CS=0xc5,
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NvBufferKind_ZF32_X24S8_MS4_1CS=0xc6,
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NvBufferKind_ZF32_X24S8_MS8_1CS=0xc7,
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NvBufferKind_ZF32_X24S8_MS16_1CS=0xc8,
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NvBufferKind_SmskedMessage=0xca,
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NvBufferKind_SmhostMessage=0xcb,
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NvBufferKind_C64_MS2_2CRA=0xcd,
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NvBufferKind_ZF32_X24S8_2CSZV=0xce,
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NvBufferKind_ZF32_X24S8_MS2_2CSZV=0xcf,
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NvBufferKind_ZF32_X24S8_MS4_2CSZV=0xd0,
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NvBufferKind_ZF32_X24S8_MS8_2CSZV=0xd1,
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NvBufferKind_ZF32_X24S8_MS16_2CSZV=0xd2,
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NvBufferKind_ZF32_X24S8_2CS=0xd3,
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NvBufferKind_ZF32_X24S8_MS2_2CS=0xd4,
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NvBufferKind_ZF32_X24S8_MS4_2CS=0xd5,
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NvBufferKind_ZF32_X24S8_MS8_2CS=0xd6,
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NvBufferKind_ZF32_X24S8_MS16_2CS=0xd7,
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NvBufferKind_C32_2C=0xd8,
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NvBufferKind_C32_2CBR=0xd9,
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NvBufferKind_C32_2CBA=0xda,
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NvBufferKind_C32_2CRA=0xdb,
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NvBufferKind_C32_2BRA=0xdc,
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NvBufferKind_C32_MS2_2C=0xdd,
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NvBufferKind_C32_MS2_2CBR=0xde,
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NvBufferKind_C32_MS2_2CRA=0xcc,
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NvBufferKind_C32_MS4_2C=0xdf,
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NvBufferKind_C32_MS4_2CBR=0xe0,
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NvBufferKind_C32_MS4_2CBA=0xe1,
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NvBufferKind_C32_MS4_2CRA=0xe2,
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NvBufferKind_C32_MS4_2BRA=0xe3,
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NvBufferKind_C32_MS8_MS16_2C=0xe4,
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NvBufferKind_C32_MS8_MS16_2CRA=0xe5,
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NvBufferKind_C64_2C=0xe6,
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NvBufferKind_C64_2CBR=0xe7,
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NvBufferKind_C64_2CBA=0xe8,
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NvBufferKind_C64_2CRA=0xe9,
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NvBufferKind_C64_2BRA=0xea,
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NvBufferKind_C64_MS2_2C=0xeb,
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NvBufferKind_C64_MS2_2CBR=0xec,
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NvBufferKind_C64_MS4_2C=0xed,
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NvBufferKind_C64_MS4_2CBR=0xee,
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NvBufferKind_C64_MS4_2CBA=0xef,
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NvBufferKind_C64_MS4_2CRA=0xf0,
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NvBufferKind_C64_MS4_2BRA=0xf1,
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NvBufferKind_C64_MS8_MS16_2C=0xf2,
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NvBufferKind_C64_MS8_MS16_2CRA=0xf3,
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NvBufferKind_C128_2C=0xf4,
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NvBufferKind_C128_2CR=0xf5,
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NvBufferKind_C128_MS2_2C=0xf6,
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NvBufferKind_C128_MS2_2CR=0xf7,
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NvBufferKind_C128_MS4_2C=0xf8,
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NvBufferKind_C128_MS4_2CR=0xf9,
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NvBufferKind_C128_MS8_MS16_2C=0xfa,
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NvBufferKind_C128_MS8_MS16_2CR=0xfb,
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NvBufferKind_X8C24=0xfc,
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NvBufferKind_PitchNoSwizzle=0xfd,
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NvBufferKind_Generic_16BX2=0xfe,
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NvBufferKind_Invalid=0xff,
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} NvBufferKind;
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typedef struct NvAddressSpace NvAddressSpace;
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typedef struct NvBuffer {
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@ -252,7 +16,7 @@ typedef struct NvBuffer {
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iova_t gpu_addr;
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iova_t gpu_addr_texture;
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NvAddressSpace* addr_space;
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NvBufferKind kind;
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NvKind kind;
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bool has_init;
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} NvBuffer;
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@ -260,14 +24,14 @@ Result nvBufferInit(void);
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u32 nvBufferGetNvmapFd(void);
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void nvBufferExit(void);
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||||
|
||||
Result nvBufferCreate(NvBuffer* m, size_t size, u32 align, NvBufferKind kind, NvAddressSpace* as);
|
||||
Result nvBufferCreateRw(NvBuffer* m, size_t size, u32 align, NvBufferKind kind, NvAddressSpace* as);
|
||||
Result nvBufferCreate(NvBuffer* m, size_t size, u32 align, NvKind kind, NvAddressSpace* as);
|
||||
Result nvBufferCreateRw(NvBuffer* m, size_t size, u32 align, NvKind kind, NvAddressSpace* as);
|
||||
void nvBufferFree(NvBuffer* m);
|
||||
|
||||
void* nvBufferGetCpuAddr(NvBuffer* m);
|
||||
iova_t nvBufferGetGpuAddr(NvBuffer* m);
|
||||
|
||||
Result nvBufferMapAsTexture(NvBuffer* m, NvBufferKind kind);
|
||||
Result nvBufferMapAsTexture(NvBuffer* m, NvKind kind);
|
||||
iova_t nvBufferGetGpuAddrTexture(NvBuffer* m);
|
||||
|
||||
Result nvBufferMakeCpuUncached(NvBuffer* m);
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
#pragma once
|
||||
#include "ioctl.h"
|
||||
#include "types.h"
|
||||
|
||||
typedef struct NvChannel {
|
||||
u32 fd;
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
#pragma once
|
||||
#include "types.h"
|
||||
|
||||
Result nvInfoInit();
|
||||
void nvInfoExit();
|
||||
Result nvInfoInit(void);
|
||||
void nvInfoExit(void);
|
||||
|
||||
u32 nvInfoGetZcullCtxSize();
|
||||
u32 nvInfoGetZcullCtxSize(void);
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
#pragma once
|
||||
#include "../types.h"
|
||||
#include "types.h"
|
||||
|
||||
// The below defines are based on Linux kernel ioctl.h.
|
||||
#define _NV_IOC_NRBITS 8
|
||||
@ -185,5 +185,3 @@ Result nvioctlChannel_GetErrorNotification(u32 fd, NvError* out);
|
||||
Result nvioctlChannel_SetPriority(u32 fd, u32 priority);
|
||||
Result nvioctlChannel_AllocGpfifoEx2(u32 fd, u32 num_entries, u32 flags, u32 unk0, u32 unk1, u32 unk2, u32 unk3, nvioctl_fence *fence_out);
|
||||
Result nvioctlChannel_SetUserData(u32 fd, void* addr);
|
||||
|
||||
typedef u64 iova_t;
|
||||
|
||||
251
nx/include/switch/nvidia/types.h
Normal file
251
nx/include/switch/nvidia/types.h
Normal file
@ -0,0 +1,251 @@
|
||||
#pragma once
|
||||
#include "../types.h"
|
||||
|
||||
typedef u64 iova_t;
|
||||
|
||||
typedef enum {
|
||||
NvLayout_Pitch = 1,
|
||||
NvLayout_Tiled = 2,
|
||||
NvLayout_BlockLinear = 3,
|
||||
} NvLayout;
|
||||
|
||||
typedef enum {
|
||||
NvDisplayScanFormat_Progressive = 0,
|
||||
NvDisplayScanFormat_Interlaced = 1,
|
||||
} NvDisplayScanFormat;
|
||||
|
||||
typedef enum {
|
||||
NvKind_Pitch = 0x0,
|
||||
NvKind_Z16 = 0x1,
|
||||
NvKind_Z16_2C = 0x2,
|
||||
NvKind_Z16_MS2_2C = 0x3,
|
||||
NvKind_Z16_MS4_2C = 0x4,
|
||||
NvKind_Z16_MS8_2C = 0x5,
|
||||
NvKind_Z16_MS16_2C = 0x6,
|
||||
NvKind_Z16_2Z = 0x7,
|
||||
NvKind_Z16_MS2_2Z = 0x8,
|
||||
NvKind_Z16_MS4_2Z = 0x9,
|
||||
NvKind_Z16_MS8_2Z = 0xa,
|
||||
NvKind_Z16_MS16_2Z = 0xb,
|
||||
NvKind_Z16_4CZ = 0xc,
|
||||
NvKind_Z16_MS2_4CZ = 0xd,
|
||||
NvKind_Z16_MS4_4CZ = 0xe,
|
||||
NvKind_Z16_MS8_4CZ = 0xf,
|
||||
NvKind_Z16_MS16_4CZ = 0x10,
|
||||
NvKind_S8Z24 = 0x11,
|
||||
NvKind_S8Z24_1Z = 0x12,
|
||||
NvKind_S8Z24_MS2_1Z = 0x13,
|
||||
NvKind_S8Z24_MS4_1Z = 0x14,
|
||||
NvKind_S8Z24_MS8_1Z = 0x15,
|
||||
NvKind_S8Z24_MS16_1Z = 0x16,
|
||||
NvKind_S8Z24_2CZ = 0x17,
|
||||
NvKind_S8Z24_MS2_2CZ = 0x18,
|
||||
NvKind_S8Z24_MS4_2CZ = 0x19,
|
||||
NvKind_S8Z24_MS8_2CZ = 0x1a,
|
||||
NvKind_S8Z24_MS16_2CZ = 0x1b,
|
||||
NvKind_S8Z24_2CS = 0x1C,
|
||||
NvKind_S8Z24_MS2_2CS = 0x1d,
|
||||
NvKind_S8Z24_MS4_2CS = 0x1e,
|
||||
NvKind_S8Z24_MS8_2CS = 0x1f,
|
||||
NvKind_S8Z24_MS16_2CS = 0x20,
|
||||
NvKind_S8Z24_4CSZV = 0x21,
|
||||
NvKind_S8Z24_MS2_4CSZV = 0x22,
|
||||
NvKind_S8Z24_MS4_4CSZV = 0x23,
|
||||
NvKind_S8Z24_MS8_4CSZV = 0x24,
|
||||
NvKind_S8Z24_MS16_4CSZV = 0x25,
|
||||
NvKind_V8Z24_MS4_VC12 = 0x26,
|
||||
NvKind_V8Z24_MS4_VC4 = 0x27,
|
||||
NvKind_V8Z24_MS8_VC8 = 0x28,
|
||||
NvKind_V8Z24_MS8_VC24 = 0x29,
|
||||
NvKind_S8 = 0x2a,
|
||||
NvKind_S8_2S = 0x2b,
|
||||
NvKind_V8Z24_MS4_VC12_1ZV = 0x2e,
|
||||
NvKind_V8Z24_MS4_VC4_1ZV = 0x2f,
|
||||
NvKind_V8Z24_MS8_VC8_1ZV = 0x30,
|
||||
NvKind_V8Z24_MS8_VC24_1ZV = 0x31,
|
||||
NvKind_V8Z24_MS4_VC12_2CS = 0x32,
|
||||
NvKind_V8Z24_MS4_VC4_2CS = 0x33,
|
||||
NvKind_V8Z24_MS8_VC8_2CS = 0x34,
|
||||
NvKind_V8Z24_MS8_VC24_2CS = 0x35,
|
||||
NvKind_V8Z24_MS4_VC12_2CZV = 0x3a,
|
||||
NvKind_V8Z24_MS4_VC4_2CZV = 0x3b,
|
||||
NvKind_V8Z24_MS8_VC8_2CZV = 0x3c,
|
||||
NvKind_V8Z24_MS8_VC24_2CZV = 0x3d,
|
||||
NvKind_V8Z24_MS4_VC12_2ZV = 0x3e,
|
||||
NvKind_V8Z24_MS4_VC4_2ZV = 0x3f,
|
||||
NvKind_V8Z24_MS8_VC8_2ZV = 0x40,
|
||||
NvKind_V8Z24_MS8_VC24_2ZV = 0x41,
|
||||
NvKind_V8Z24_MS4_VC12_4CSZV = 0x42,
|
||||
NvKind_V8Z24_MS4_VC4_4CSZV = 0x43,
|
||||
NvKind_V8Z24_MS8_VC8_4CSZV = 0x44,
|
||||
NvKind_V8Z24_MS8_VC24_4CSZV = 0x45,
|
||||
NvKind_Z24S8 = 0x46,
|
||||
NvKind_Z24S8_1Z = 0x47,
|
||||
NvKind_Z24S8_MS2_1Z = 0x48,
|
||||
NvKind_Z24S8_MS4_1Z = 0x49,
|
||||
NvKind_Z24S8_MS8_1Z = 0x4a,
|
||||
NvKind_Z24S8_MS16_1Z = 0x4b,
|
||||
NvKind_Z24S8_2CS = 0x4c,
|
||||
NvKind_Z24S8_MS2_2CS = 0x4d,
|
||||
NvKind_Z24S8_MS4_2CS = 0x4e,
|
||||
NvKind_Z24S8_MS8_2CS = 0x4f,
|
||||
NvKind_Z24S8_MS16_2CS = 0x50,
|
||||
NvKind_Z24S8_2CZ = 0x51,
|
||||
NvKind_Z24S8_MS2_2CZ = 0x52,
|
||||
NvKind_Z24S8_MS4_2CZ = 0x53,
|
||||
NvKind_Z24S8_MS8_2CZ = 0x54,
|
||||
NvKind_Z24S8_MS16_2CZ = 0x55,
|
||||
NvKind_Z24S8_4CSZV = 0x56,
|
||||
NvKind_Z24S8_MS2_4CSZV = 0x57,
|
||||
NvKind_Z24S8_MS4_4CSZV = 0x58,
|
||||
NvKind_Z24S8_MS8_4CSZV = 0x59,
|
||||
NvKind_Z24S8_MS16_4CSZV = 0x5a,
|
||||
NvKind_Z24V8_MS4_VC12 = 0x5b,
|
||||
NvKind_Z24V8_MS4_VC4 = 0x5C,
|
||||
NvKind_Z24V8_MS8_VC8 = 0x5d,
|
||||
NvKind_Z24V8_MS8_VC24 = 0x5e,
|
||||
NvKind_Z24V8_MS4_VC12_1ZV = 0x63,
|
||||
NvKind_Z24V8_MS4_VC4_1ZV = 0x64,
|
||||
NvKind_Z24V8_MS8_VC8_1ZV = 0x65,
|
||||
NvKind_Z24V8_MS8_VC24_1ZV = 0x66,
|
||||
NvKind_Z24V8_MS4_VC12_2CS = 0x67,
|
||||
NvKind_Z24V8_MS4_VC4_2CS = 0x68,
|
||||
NvKind_Z24V8_MS8_VC8_2CS = 0x69,
|
||||
NvKind_Z24V8_MS8_VC24_2CS = 0x6a,
|
||||
NvKind_Z24V8_MS4_VC12_2CZV = 0x6f,
|
||||
NvKind_Z24V8_MS4_VC4_2CZV = 0x70,
|
||||
NvKind_Z24V8_MS8_VC8_2CZV = 0x71,
|
||||
NvKind_Z24V8_MS8_VC24_2CZV = 0x72,
|
||||
NvKind_Z24V8_MS4_VC12_2ZV = 0x73,
|
||||
NvKind_Z24V8_MS4_VC4_2ZV = 0x74,
|
||||
NvKind_Z24V8_MS8_VC8_2ZV = 0x75,
|
||||
NvKind_Z24V8_MS8_VC24_2ZV = 0x76,
|
||||
NvKind_Z24V8_MS4_VC12_4CSZV = 0x77,
|
||||
NvKind_Z24V8_MS4_VC4_4CSZV = 0x78,
|
||||
NvKind_Z24V8_MS8_VC8_4CSZV = 0x79,
|
||||
NvKind_Z24V8_MS8_VC24_4CSZV = 0x7a,
|
||||
NvKind_ZF32 = 0x7b,
|
||||
NvKind_ZF32_1Z = 0x7C,
|
||||
NvKind_ZF32_MS2_1Z = 0x7d,
|
||||
NvKind_ZF32_MS4_1Z = 0x7e,
|
||||
NvKind_ZF32_MS8_1Z = 0x7f,
|
||||
NvKind_ZF32_MS16_1Z = 0x80,
|
||||
NvKind_ZF32_2CS = 0x81,
|
||||
NvKind_ZF32_MS2_2CS = 0x82,
|
||||
NvKind_ZF32_MS4_2CS = 0x83,
|
||||
NvKind_ZF32_MS8_2CS = 0x84,
|
||||
NvKind_ZF32_MS16_2CS = 0x85,
|
||||
NvKind_ZF32_2CZ = 0x86,
|
||||
NvKind_ZF32_MS2_2CZ = 0x87,
|
||||
NvKind_ZF32_MS4_2CZ = 0x88,
|
||||
NvKind_ZF32_MS8_2CZ = 0x89,
|
||||
NvKind_ZF32_MS16_2CZ = 0x8a,
|
||||
NvKind_X8Z24_X16V8S8_MS4_VC12 = 0x8b,
|
||||
NvKind_X8Z24_X16V8S8_MS4_VC4 = 0x8c,
|
||||
NvKind_X8Z24_X16V8S8_MS8_VC8 = 0x8d,
|
||||
NvKind_X8Z24_X16V8S8_MS8_VC24 = 0x8e,
|
||||
NvKind_X8Z24_X16V8S8_MS4_VC12_1CS = 0x8f,
|
||||
NvKind_X8Z24_X16V8S8_MS4_VC4_1CS = 0x90,
|
||||
NvKind_X8Z24_X16V8S8_MS8_VC8_1CS = 0x91,
|
||||
NvKind_X8Z24_X16V8S8_MS8_VC24_1CS = 0x92,
|
||||
NvKind_X8Z24_X16V8S8_MS4_VC12_1ZV = 0x97,
|
||||
NvKind_X8Z24_X16V8S8_MS4_VC4_1ZV = 0x98,
|
||||
NvKind_X8Z24_X16V8S8_MS8_VC8_1ZV = 0x99,
|
||||
NvKind_X8Z24_X16V8S8_MS8_VC24_1ZV = 0x9a,
|
||||
NvKind_X8Z24_X16V8S8_MS4_VC12_1CZV = 0x9b,
|
||||
NvKind_X8Z24_X16V8S8_MS4_VC4_1CZV = 0x9c,
|
||||
NvKind_X8Z24_X16V8S8_MS8_VC8_1CZV = 0x9d,
|
||||
NvKind_X8Z24_X16V8S8_MS8_VC24_1CZV = 0x9e,
|
||||
NvKind_X8Z24_X16V8S8_MS4_VC12_2CS = 0x9f,
|
||||
NvKind_X8Z24_X16V8S8_MS4_VC4_2CS = 0xa0,
|
||||
NvKind_X8Z24_X16V8S8_MS8_VC8_2CS = 0xa1,
|
||||
NvKind_X8Z24_X16V8S8_MS8_VC24_2CS = 0xa2,
|
||||
NvKind_X8Z24_X16V8S8_MS4_VC12_2CSZV = 0xa3,
|
||||
NvKind_X8Z24_X16V8S8_MS4_VC4_2CSZV = 0xa4,
|
||||
NvKind_X8Z24_X16V8S8_MS8_VC8_2CSZV = 0xa5,
|
||||
NvKind_X8Z24_X16V8S8_MS8_VC24_2CSZV = 0xa6,
|
||||
NvKind_ZF32_X16V8S8_MS4_VC12 = 0xa7,
|
||||
NvKind_ZF32_X16V8S8_MS4_VC4 = 0xa8,
|
||||
NvKind_ZF32_X16V8S8_MS8_VC8 = 0xa9,
|
||||
NvKind_ZF32_X16V8S8_MS8_VC24 = 0xaa,
|
||||
NvKind_ZF32_X16V8S8_MS4_VC12_1CS = 0xab,
|
||||
NvKind_ZF32_X16V8S8_MS4_VC4_1CS = 0xac,
|
||||
NvKind_ZF32_X16V8S8_MS8_VC8_1CS = 0xad,
|
||||
NvKind_ZF32_X16V8S8_MS8_VC24_1CS = 0xae,
|
||||
NvKind_ZF32_X16V8S8_MS4_VC12_1ZV = 0xb3,
|
||||
NvKind_ZF32_X16V8S8_MS4_VC4_1ZV = 0xb4,
|
||||
NvKind_ZF32_X16V8S8_MS8_VC8_1ZV = 0xb5,
|
||||
NvKind_ZF32_X16V8S8_MS8_VC24_1ZV = 0xb6,
|
||||
NvKind_ZF32_X16V8S8_MS4_VC12_1CZV = 0xb7,
|
||||
NvKind_ZF32_X16V8S8_MS4_VC4_1CZV = 0xb8,
|
||||
NvKind_ZF32_X16V8S8_MS8_VC8_1CZV = 0xb9,
|
||||
NvKind_ZF32_X16V8S8_MS8_VC24_1CZV = 0xba,
|
||||
NvKind_ZF32_X16V8S8_MS4_VC12_2CS = 0xbb,
|
||||
NvKind_ZF32_X16V8S8_MS4_VC4_2CS = 0xbc,
|
||||
NvKind_ZF32_X16V8S8_MS8_VC8_2CS = 0xbd,
|
||||
NvKind_ZF32_X16V8S8_MS8_VC24_2CS = 0xbe,
|
||||
NvKind_ZF32_X16V8S8_MS4_VC12_2CSZV = 0xbf,
|
||||
NvKind_ZF32_X16V8S8_MS4_VC4_2CSZV = 0xc0,
|
||||
NvKind_ZF32_X16V8S8_MS8_VC8_2CSZV = 0xc1,
|
||||
NvKind_ZF32_X16V8S8_MS8_VC24_2CSZV = 0xc2,
|
||||
NvKind_ZF32_X24S8 = 0xc3,
|
||||
NvKind_ZF32_X24S8_1CS = 0xc4,
|
||||
NvKind_ZF32_X24S8_MS2_1CS = 0xc5,
|
||||
NvKind_ZF32_X24S8_MS4_1CS = 0xc6,
|
||||
NvKind_ZF32_X24S8_MS8_1CS = 0xc7,
|
||||
NvKind_ZF32_X24S8_MS16_1CS = 0xc8,
|
||||
NvKind_SmskedMessage = 0xca,
|
||||
NvKind_SmhostMessage = 0xcb,
|
||||
NvKind_C64_MS2_2CRA = 0xcd,
|
||||
NvKind_ZF32_X24S8_2CSZV = 0xce,
|
||||
NvKind_ZF32_X24S8_MS2_2CSZV = 0xcf,
|
||||
NvKind_ZF32_X24S8_MS4_2CSZV = 0xd0,
|
||||
NvKind_ZF32_X24S8_MS8_2CSZV = 0xd1,
|
||||
NvKind_ZF32_X24S8_MS16_2CSZV = 0xd2,
|
||||
NvKind_ZF32_X24S8_2CS = 0xd3,
|
||||
NvKind_ZF32_X24S8_MS2_2CS = 0xd4,
|
||||
NvKind_ZF32_X24S8_MS4_2CS = 0xd5,
|
||||
NvKind_ZF32_X24S8_MS8_2CS = 0xd6,
|
||||
NvKind_ZF32_X24S8_MS16_2CS = 0xd7,
|
||||
NvKind_C32_2C = 0xd8,
|
||||
NvKind_C32_2CBR = 0xd9,
|
||||
NvKind_C32_2CBA = 0xda,
|
||||
NvKind_C32_2CRA = 0xdb,
|
||||
NvKind_C32_2BRA = 0xdc,
|
||||
NvKind_C32_MS2_2C = 0xdd,
|
||||
NvKind_C32_MS2_2CBR = 0xde,
|
||||
NvKind_C32_MS2_2CRA = 0xcc,
|
||||
NvKind_C32_MS4_2C = 0xdf,
|
||||
NvKind_C32_MS4_2CBR = 0xe0,
|
||||
NvKind_C32_MS4_2CBA = 0xe1,
|
||||
NvKind_C32_MS4_2CRA = 0xe2,
|
||||
NvKind_C32_MS4_2BRA = 0xe3,
|
||||
NvKind_C32_MS8_MS16_2C = 0xe4,
|
||||
NvKind_C32_MS8_MS16_2CRA = 0xe5,
|
||||
NvKind_C64_2C = 0xe6,
|
||||
NvKind_C64_2CBR = 0xe7,
|
||||
NvKind_C64_2CBA = 0xe8,
|
||||
NvKind_C64_2CRA = 0xe9,
|
||||
NvKind_C64_2BRA = 0xea,
|
||||
NvKind_C64_MS2_2C = 0xeb,
|
||||
NvKind_C64_MS2_2CBR = 0xec,
|
||||
NvKind_C64_MS4_2C = 0xed,
|
||||
NvKind_C64_MS4_2CBR = 0xee,
|
||||
NvKind_C64_MS4_2CBA = 0xef,
|
||||
NvKind_C64_MS4_2CRA = 0xf0,
|
||||
NvKind_C64_MS4_2BRA = 0xf1,
|
||||
NvKind_C64_MS8_MS16_2C = 0xf2,
|
||||
NvKind_C64_MS8_MS16_2CRA = 0xf3,
|
||||
NvKind_C128_2C = 0xf4,
|
||||
NvKind_C128_2CR = 0xf5,
|
||||
NvKind_C128_MS2_2C = 0xf6,
|
||||
NvKind_C128_MS2_2CR = 0xf7,
|
||||
NvKind_C128_MS4_2C = 0xf8,
|
||||
NvKind_C128_MS4_2CR = 0xf9,
|
||||
NvKind_C128_MS8_MS16_2C = 0xfa,
|
||||
NvKind_C128_MS8_MS16_2CR = 0xfb,
|
||||
NvKind_X8C24 = 0xfc,
|
||||
NvKind_PitchNoSwizzle = 0xfd,
|
||||
NvKind_Generic_16BX2 = 0xfe,
|
||||
NvKind_Invalid = 0xff,
|
||||
} NvKind;
|
||||
@ -56,7 +56,7 @@ Result nvAddressSpaceReserveFull(NvAddressSpace* a) {
|
||||
}
|
||||
|
||||
Result nvAddressSpaceMapBuffer(
|
||||
NvAddressSpace* a, u32 fd, NvBufferKind kind,
|
||||
NvAddressSpace* a, u32 fd, NvKind kind,
|
||||
iova_t* iova_out) {
|
||||
return nvioctlNvhostAsGpu_MapBufferEx(
|
||||
a->fd, NvMapBufferFlags_IsCachable, kind, fd, 0x10000, 0, 0, 0, iova_out);
|
||||
|
||||
@ -42,7 +42,7 @@ u32 nvBufferGetNvmapFd(void) {
|
||||
}
|
||||
|
||||
static Result _nvBufferCreate(
|
||||
NvBuffer* m, size_t size, u32 flags, u32 align, NvBufferKind kind,
|
||||
NvBuffer* m, size_t size, u32 flags, u32 align, NvKind kind,
|
||||
NvAddressSpace* as)
|
||||
{
|
||||
Result rc;
|
||||
@ -80,12 +80,12 @@ static Result _nvBufferCreate(
|
||||
}
|
||||
|
||||
Result nvBufferCreate(
|
||||
NvBuffer* m, size_t size, u32 align, NvBufferKind kind, NvAddressSpace* as) {
|
||||
NvBuffer* m, size_t size, u32 align, NvKind kind, NvAddressSpace* as) {
|
||||
return _nvBufferCreate(m, size, 0, align, kind, as);
|
||||
}
|
||||
|
||||
Result nvBufferCreateRw(
|
||||
NvBuffer* m, size_t size, u32 align, NvBufferKind kind, NvAddressSpace* as) {
|
||||
NvBuffer* m, size_t size, u32 align, NvKind kind, NvAddressSpace* as) {
|
||||
return _nvBufferCreate(m, size, NvBufferFlags_Writable, align, kind, as);
|
||||
}
|
||||
|
||||
@ -123,7 +123,7 @@ iova_t nvBufferGetGpuAddr(NvBuffer* m) {
|
||||
return m->gpu_addr;
|
||||
}
|
||||
|
||||
Result nvBufferMapAsTexture(NvBuffer* m, NvBufferKind kind) {
|
||||
Result nvBufferMapAsTexture(NvBuffer* m, NvKind kind) {
|
||||
return nvAddressSpaceMapBuffer(m->addr_space, m->fd, kind, &m->gpu_addr_texture);
|
||||
}
|
||||
|
||||
|
||||
@ -22,7 +22,7 @@ Result nvCmdListCreate(NvCmdList* c, NvGpu* parent, size_t max_cmds)
|
||||
Result rc;
|
||||
|
||||
rc = nvBufferCreate(
|
||||
&c->buffer, max_cmds * 4, 0x1000, NvBufferKind_Pitch,
|
||||
&c->buffer, max_cmds * 4, 0x1000, NvKind_Pitch,
|
||||
&parent->addr_space);
|
||||
|
||||
if (R_SUCCEEDED(rc)) {
|
||||
|
||||
@ -25,11 +25,11 @@ Result nvZcullContextCreate(NvZcullContext* z, NvGpu* parent)
|
||||
z->parent = parent;
|
||||
|
||||
rc = nvBufferCreateRw(
|
||||
&z->ctx_buf, nvInfoGetZcullCtxSize(), 0x20000, NvBufferKind_Pitch,
|
||||
&z->ctx_buf, nvInfoGetZcullCtxSize(), 0x20000, NvKind_Pitch,
|
||||
&parent->addr_space);
|
||||
|
||||
if (R_SUCCEEDED(rc))
|
||||
rc = nvBufferMapAsTexture(&z->ctx_buf, NvBufferKind_Generic_16BX2);
|
||||
rc = nvBufferMapAsTexture(&z->ctx_buf, NvKind_Generic_16BX2);
|
||||
|
||||
if (R_SUCCEEDED(rc))
|
||||
rc = nvioctlChannel_ZCullBind(
|
||||
|
||||
Loading…
Reference in New Issue
Block a user