From 30e2ca8ec3a81a52888e9791ae34c846b0d9d2b7 Mon Sep 17 00:00:00 2001 From: fincs Date: Tue, 28 Aug 2018 14:17:41 +0200 Subject: [PATCH] Introduce nvidia/types.h & move NvBufferKind to it (renamed to NvKind) --- nx/include/switch/nvidia/address_space.h | 3 +- nx/include/switch/nvidia/buffer.h | 248 +--------------------- nx/include/switch/nvidia/channel.h | 2 +- nx/include/switch/nvidia/info.h | 7 +- nx/include/switch/nvidia/ioctl.h | 4 +- nx/include/switch/nvidia/types.h | 251 +++++++++++++++++++++++ nx/source/nvidia/address_space.c | 2 +- nx/source/nvidia/buffer.c | 8 +- nx/source/nvidia/gpu/cmd_list.c | 2 +- nx/source/nvidia/gpu/zcull_ctx.c | 4 +- 10 files changed, 273 insertions(+), 258 deletions(-) create mode 100644 nx/include/switch/nvidia/types.h diff --git a/nx/include/switch/nvidia/address_space.h b/nx/include/switch/nvidia/address_space.h index 1b3a8e5f..0a28fc39 100644 --- a/nx/include/switch/nvidia/address_space.h +++ b/nx/include/switch/nvidia/address_space.h @@ -1,4 +1,5 @@ #pragma once +#include "types.h" typedef struct NvAddressSpace { u32 fd; @@ -17,7 +18,7 @@ Result nvAddressSpaceReserveAlign(NvAddressSpace* a, NvPageSize align, u32 pages Result nvAddressSpaceReserveAtFixedAddr(NvAddressSpace* a, iova_t addr, u32 pages, NvPageSize page_sz); Result nvAddressSpaceReserveFull(NvAddressSpace* a); -Result nvAddressSpaceMapBuffer(NvAddressSpace* a, u32 fd, NvBufferKind kind, iova_t* iova_out); +Result nvAddressSpaceMapBuffer(NvAddressSpace* a, u32 fd, NvKind kind, iova_t* iova_out); struct NvChannel; Result nvAddressSpaceBindToChannel(NvAddressSpace* a, struct NvChannel* channel); diff --git a/nx/include/switch/nvidia/buffer.h b/nx/include/switch/nvidia/buffer.h index 29d17835..8a4c04db 100644 --- a/nx/include/switch/nvidia/buffer.h +++ b/nx/include/switch/nvidia/buffer.h @@ -1,248 +1,12 @@ #pragma once - -#include "../types.h" +#include "types.h" +#include "address_space.h" typedef enum { NvBufferFlags_Writable=1, NvBufferFlags_Nintendo=0x20000, } NvBufferFlags; -typedef enum { - NvBufferKind_Pitch=0x0, - NvBufferKind_Z16=0x1, - NvBufferKind_Z16_2C=0x2, - NvBufferKind_Z16_MS2_2C=0x3, - NvBufferKind_Z16_MS4_2C=0x4, - NvBufferKind_Z16_MS8_2C=0x5, - NvBufferKind_Z16_MS16_2C=0x6, - NvBufferKind_Z16_2Z=0x7, - NvBufferKind_Z16_MS2_2Z=0x8, - NvBufferKind_Z16_MS4_2Z=0x9, - NvBufferKind_Z16_MS8_2Z=0xa, - NvBufferKind_Z16_MS16_2Z=0xb, - NvBufferKind_Z16_4CZ=0xc, - NvBufferKind_Z16_MS2_4CZ=0xd, - NvBufferKind_Z16_MS4_4CZ=0xe, - NvBufferKind_Z16_MS8_4CZ=0xf, - NvBufferKind_Z16_MS16_4CZ=0x10, - NvBufferKind_S8Z24=0x11, - NvBufferKind_S8Z24_1Z=0x12, - NvBufferKind_S8Z24_MS2_1Z=0x13, - NvBufferKind_S8Z24_MS4_1Z=0x14, - NvBufferKind_S8Z24_MS8_1Z=0x15, - NvBufferKind_S8Z24_MS16_1Z=0x16, - NvBufferKind_S8Z24_2CZ=0x17, - NvBufferKind_S8Z24_MS2_2CZ=0x18, - NvBufferKind_S8Z24_MS4_2CZ=0x19, - NvBufferKind_S8Z24_MS8_2CZ=0x1a, - NvBufferKind_S8Z24_MS16_2CZ=0x1b, - NvBufferKind_S8Z24_2CS=0x1C, - NvBufferKind_S8Z24_MS2_2CS=0x1d, - NvBufferKind_S8Z24_MS4_2CS=0x1e, - NvBufferKind_S8Z24_MS8_2CS=0x1f, - NvBufferKind_S8Z24_MS16_2CS=0x20, - NvBufferKind_S8Z24_4CSZV=0x21, - NvBufferKind_S8Z24_MS2_4CSZV=0x22, - NvBufferKind_S8Z24_MS4_4CSZV=0x23, - NvBufferKind_S8Z24_MS8_4CSZV=0x24, - NvBufferKind_S8Z24_MS16_4CSZV=0x25, - NvBufferKind_V8Z24_MS4_VC12=0x26, - NvBufferKind_V8Z24_MS4_VC4=0x27, - NvBufferKind_V8Z24_MS8_VC8=0x28, - NvBufferKind_V8Z24_MS8_VC24=0x29, - NvBufferKind_S8=0x2a, - NvBufferKind_S8_2S=0x2b, - NvBufferKind_V8Z24_MS4_VC12_1ZV=0x2e, - NvBufferKind_V8Z24_MS4_VC4_1ZV=0x2f, - NvBufferKind_V8Z24_MS8_VC8_1ZV=0x30, - NvBufferKind_V8Z24_MS8_VC24_1ZV=0x31, - NvBufferKind_V8Z24_MS4_VC12_2CS=0x32, - NvBufferKind_V8Z24_MS4_VC4_2CS=0x33, - NvBufferKind_V8Z24_MS8_VC8_2CS=0x34, - NvBufferKind_V8Z24_MS8_VC24_2CS=0x35, - NvBufferKind_V8Z24_MS4_VC12_2CZV=0x3a, - NvBufferKind_V8Z24_MS4_VC4_2CZV=0x3b, - NvBufferKind_V8Z24_MS8_VC8_2CZV=0x3c, - NvBufferKind_V8Z24_MS8_VC24_2CZV=0x3d, - NvBufferKind_V8Z24_MS4_VC12_2ZV=0x3e, - NvBufferKind_V8Z24_MS4_VC4_2ZV=0x3f, - NvBufferKind_V8Z24_MS8_VC8_2ZV=0x40, - NvBufferKind_V8Z24_MS8_VC24_2ZV=0x41, - NvBufferKind_V8Z24_MS4_VC12_4CSZV=0x42, - NvBufferKind_V8Z24_MS4_VC4_4CSZV=0x43, - NvBufferKind_V8Z24_MS8_VC8_4CSZV=0x44, - NvBufferKind_V8Z24_MS8_VC24_4CSZV=0x45, - NvBufferKind_Z24S8=0x46, - NvBufferKind_Z24S8_1Z=0x47, - NvBufferKind_Z24S8_MS2_1Z=0x48, - NvBufferKind_Z24S8_MS4_1Z=0x49, - NvBufferKind_Z24S8_MS8_1Z=0x4a, - NvBufferKind_Z24S8_MS16_1Z=0x4b, - NvBufferKind_Z24S8_2CS=0x4c, - NvBufferKind_Z24S8_MS2_2CS=0x4d, - NvBufferKind_Z24S8_MS4_2CS=0x4e, - NvBufferKind_Z24S8_MS8_2CS=0x4f, - NvBufferKind_Z24S8_MS16_2CS=0x50, - NvBufferKind_Z24S8_2CZ=0x51, - NvBufferKind_Z24S8_MS2_2CZ=0x52, - NvBufferKind_Z24S8_MS4_2CZ=0x53, - NvBufferKind_Z24S8_MS8_2CZ=0x54, - NvBufferKind_Z24S8_MS16_2CZ=0x55, - NvBufferKind_Z24S8_4CSZV=0x56, - NvBufferKind_Z24S8_MS2_4CSZV=0x57, - NvBufferKind_Z24S8_MS4_4CSZV=0x58, - NvBufferKind_Z24S8_MS8_4CSZV=0x59, - NvBufferKind_Z24S8_MS16_4CSZV=0x5a, - NvBufferKind_Z24V8_MS4_VC12=0x5b, - NvBufferKind_Z24V8_MS4_VC4=0x5C, - NvBufferKind_Z24V8_MS8_VC8=0x5d, - NvBufferKind_Z24V8_MS8_VC24=0x5e, - NvBufferKind_Z24V8_MS4_VC12_1ZV=0x63, - NvBufferKind_Z24V8_MS4_VC4_1ZV=0x64, - NvBufferKind_Z24V8_MS8_VC8_1ZV=0x65, - NvBufferKind_Z24V8_MS8_VC24_1ZV=0x66, - NvBufferKind_Z24V8_MS4_VC12_2CS=0x67, - NvBufferKind_Z24V8_MS4_VC4_2CS=0x68, - NvBufferKind_Z24V8_MS8_VC8_2CS=0x69, - NvBufferKind_Z24V8_MS8_VC24_2CS=0x6a, - NvBufferKind_Z24V8_MS4_VC12_2CZV=0x6f, - NvBufferKind_Z24V8_MS4_VC4_2CZV=0x70, - NvBufferKind_Z24V8_MS8_VC8_2CZV=0x71, - NvBufferKind_Z24V8_MS8_VC24_2CZV=0x72, - NvBufferKind_Z24V8_MS4_VC12_2ZV=0x73, - NvBufferKind_Z24V8_MS4_VC4_2ZV=0x74, - NvBufferKind_Z24V8_MS8_VC8_2ZV=0x75, - NvBufferKind_Z24V8_MS8_VC24_2ZV=0x76, - NvBufferKind_Z24V8_MS4_VC12_4CSZV=0x77, - NvBufferKind_Z24V8_MS4_VC4_4CSZV=0x78, - NvBufferKind_Z24V8_MS8_VC8_4CSZV=0x79, - NvBufferKind_Z24V8_MS8_VC24_4CSZV=0x7a, - NvBufferKind_ZF32=0x7b, - NvBufferKind_ZF32_1Z=0x7C, - NvBufferKind_ZF32_MS2_1Z=0x7d, - NvBufferKind_ZF32_MS4_1Z=0x7e, - NvBufferKind_ZF32_MS8_1Z=0x7f, - NvBufferKind_ZF32_MS16_1Z=0x80, - NvBufferKind_ZF32_2CS=0x81, - NvBufferKind_ZF32_MS2_2CS=0x82, - NvBufferKind_ZF32_MS4_2CS=0x83, - NvBufferKind_ZF32_MS8_2CS=0x84, - NvBufferKind_ZF32_MS16_2CS=0x85, - NvBufferKind_ZF32_2CZ=0x86, - NvBufferKind_ZF32_MS2_2CZ=0x87, - NvBufferKind_ZF32_MS4_2CZ=0x88, - NvBufferKind_ZF32_MS8_2CZ=0x89, - NvBufferKind_ZF32_MS16_2CZ=0x8a, - NvBufferKind_X8Z24_X16V8S8_MS4_VC12=0x8b, - NvBufferKind_X8Z24_X16V8S8_MS4_VC4=0x8c, - NvBufferKind_X8Z24_X16V8S8_MS8_VC8=0x8d, - NvBufferKind_X8Z24_X16V8S8_MS8_VC24=0x8e, - NvBufferKind_X8Z24_X16V8S8_MS4_VC12_1CS=0x8f, - NvBufferKind_X8Z24_X16V8S8_MS4_VC4_1CS=0x90, - NvBufferKind_X8Z24_X16V8S8_MS8_VC8_1CS=0x91, - NvBufferKind_X8Z24_X16V8S8_MS8_VC24_1CS=0x92, - NvBufferKind_X8Z24_X16V8S8_MS4_VC12_1ZV=0x97, - NvBufferKind_X8Z24_X16V8S8_MS4_VC4_1ZV=0x98, - NvBufferKind_X8Z24_X16V8S8_MS8_VC8_1ZV=0x99, - NvBufferKind_X8Z24_X16V8S8_MS8_VC24_1ZV=0x9a, - NvBufferKind_X8Z24_X16V8S8_MS4_VC12_1CZV=0x9b, - NvBufferKind_X8Z24_X16V8S8_MS4_VC4_1CZV=0x9c, - NvBufferKind_X8Z24_X16V8S8_MS8_VC8_1CZV=0x9d, - NvBufferKind_X8Z24_X16V8S8_MS8_VC24_1CZV=0x9e, - NvBufferKind_X8Z24_X16V8S8_MS4_VC12_2CS=0x9f, - NvBufferKind_X8Z24_X16V8S8_MS4_VC4_2CS=0xa0, - NvBufferKind_X8Z24_X16V8S8_MS8_VC8_2CS=0xa1, - NvBufferKind_X8Z24_X16V8S8_MS8_VC24_2CS=0xa2, - NvBufferKind_X8Z24_X16V8S8_MS4_VC12_2CSZV=0xa3, - NvBufferKind_X8Z24_X16V8S8_MS4_VC4_2CSZV=0xa4, - NvBufferKind_X8Z24_X16V8S8_MS8_VC8_2CSZV=0xa5, - NvBufferKind_X8Z24_X16V8S8_MS8_VC24_2CSZV=0xa6, - NvBufferKind_ZF32_X16V8S8_MS4_VC12=0xa7, - NvBufferKind_ZF32_X16V8S8_MS4_VC4=0xa8, - NvBufferKind_ZF32_X16V8S8_MS8_VC8=0xa9, - NvBufferKind_ZF32_X16V8S8_MS8_VC24=0xaa, - NvBufferKind_ZF32_X16V8S8_MS4_VC12_1CS=0xab, - NvBufferKind_ZF32_X16V8S8_MS4_VC4_1CS=0xac, - NvBufferKind_ZF32_X16V8S8_MS8_VC8_1CS=0xad, - NvBufferKind_ZF32_X16V8S8_MS8_VC24_1CS=0xae, - NvBufferKind_ZF32_X16V8S8_MS4_VC12_1ZV=0xb3, - NvBufferKind_ZF32_X16V8S8_MS4_VC4_1ZV=0xb4, - NvBufferKind_ZF32_X16V8S8_MS8_VC8_1ZV=0xb5, - NvBufferKind_ZF32_X16V8S8_MS8_VC24_1ZV=0xb6, - NvBufferKind_ZF32_X16V8S8_MS4_VC12_1CZV=0xb7, - NvBufferKind_ZF32_X16V8S8_MS4_VC4_1CZV=0xb8, - NvBufferKind_ZF32_X16V8S8_MS8_VC8_1CZV=0xb9, - NvBufferKind_ZF32_X16V8S8_MS8_VC24_1CZV=0xba, - NvBufferKind_ZF32_X16V8S8_MS4_VC12_2CS=0xbb, - NvBufferKind_ZF32_X16V8S8_MS4_VC4_2CS=0xbc, - NvBufferKind_ZF32_X16V8S8_MS8_VC8_2CS=0xbd, - NvBufferKind_ZF32_X16V8S8_MS8_VC24_2CS=0xbe, - NvBufferKind_ZF32_X16V8S8_MS4_VC12_2CSZV=0xbf, - NvBufferKind_ZF32_X16V8S8_MS4_VC4_2CSZV=0xc0, - NvBufferKind_ZF32_X16V8S8_MS8_VC8_2CSZV=0xc1, - NvBufferKind_ZF32_X16V8S8_MS8_VC24_2CSZV=0xc2, - NvBufferKind_ZF32_X24S8=0xc3, - NvBufferKind_ZF32_X24S8_1CS=0xc4, - NvBufferKind_ZF32_X24S8_MS2_1CS=0xc5, - NvBufferKind_ZF32_X24S8_MS4_1CS=0xc6, - NvBufferKind_ZF32_X24S8_MS8_1CS=0xc7, - NvBufferKind_ZF32_X24S8_MS16_1CS=0xc8, - NvBufferKind_SmskedMessage=0xca, - NvBufferKind_SmhostMessage=0xcb, - NvBufferKind_C64_MS2_2CRA=0xcd, - NvBufferKind_ZF32_X24S8_2CSZV=0xce, - NvBufferKind_ZF32_X24S8_MS2_2CSZV=0xcf, - NvBufferKind_ZF32_X24S8_MS4_2CSZV=0xd0, - NvBufferKind_ZF32_X24S8_MS8_2CSZV=0xd1, - NvBufferKind_ZF32_X24S8_MS16_2CSZV=0xd2, - NvBufferKind_ZF32_X24S8_2CS=0xd3, - NvBufferKind_ZF32_X24S8_MS2_2CS=0xd4, - NvBufferKind_ZF32_X24S8_MS4_2CS=0xd5, - NvBufferKind_ZF32_X24S8_MS8_2CS=0xd6, - NvBufferKind_ZF32_X24S8_MS16_2CS=0xd7, - NvBufferKind_C32_2C=0xd8, - NvBufferKind_C32_2CBR=0xd9, - NvBufferKind_C32_2CBA=0xda, - NvBufferKind_C32_2CRA=0xdb, - NvBufferKind_C32_2BRA=0xdc, - NvBufferKind_C32_MS2_2C=0xdd, - NvBufferKind_C32_MS2_2CBR=0xde, - NvBufferKind_C32_MS2_2CRA=0xcc, - NvBufferKind_C32_MS4_2C=0xdf, - NvBufferKind_C32_MS4_2CBR=0xe0, - NvBufferKind_C32_MS4_2CBA=0xe1, - NvBufferKind_C32_MS4_2CRA=0xe2, - NvBufferKind_C32_MS4_2BRA=0xe3, - NvBufferKind_C32_MS8_MS16_2C=0xe4, - NvBufferKind_C32_MS8_MS16_2CRA=0xe5, - NvBufferKind_C64_2C=0xe6, - NvBufferKind_C64_2CBR=0xe7, - NvBufferKind_C64_2CBA=0xe8, - NvBufferKind_C64_2CRA=0xe9, - NvBufferKind_C64_2BRA=0xea, - NvBufferKind_C64_MS2_2C=0xeb, - NvBufferKind_C64_MS2_2CBR=0xec, - NvBufferKind_C64_MS4_2C=0xed, - NvBufferKind_C64_MS4_2CBR=0xee, - NvBufferKind_C64_MS4_2CBA=0xef, - NvBufferKind_C64_MS4_2CRA=0xf0, - NvBufferKind_C64_MS4_2BRA=0xf1, - NvBufferKind_C64_MS8_MS16_2C=0xf2, - NvBufferKind_C64_MS8_MS16_2CRA=0xf3, - NvBufferKind_C128_2C=0xf4, - NvBufferKind_C128_2CR=0xf5, - NvBufferKind_C128_MS2_2C=0xf6, - NvBufferKind_C128_MS2_2CR=0xf7, - NvBufferKind_C128_MS4_2C=0xf8, - NvBufferKind_C128_MS4_2CR=0xf9, - NvBufferKind_C128_MS8_MS16_2C=0xfa, - NvBufferKind_C128_MS8_MS16_2CR=0xfb, - NvBufferKind_X8C24=0xfc, - NvBufferKind_PitchNoSwizzle=0xfd, - NvBufferKind_Generic_16BX2=0xfe, - NvBufferKind_Invalid=0xff, -} NvBufferKind; - typedef struct NvAddressSpace NvAddressSpace; typedef struct NvBuffer { @@ -252,7 +16,7 @@ typedef struct NvBuffer { iova_t gpu_addr; iova_t gpu_addr_texture; NvAddressSpace* addr_space; - NvBufferKind kind; + NvKind kind; bool has_init; } NvBuffer; @@ -260,14 +24,14 @@ Result nvBufferInit(void); u32 nvBufferGetNvmapFd(void); void nvBufferExit(void); -Result nvBufferCreate(NvBuffer* m, size_t size, u32 align, NvBufferKind kind, NvAddressSpace* as); -Result nvBufferCreateRw(NvBuffer* m, size_t size, u32 align, NvBufferKind kind, NvAddressSpace* as); +Result nvBufferCreate(NvBuffer* m, size_t size, u32 align, NvKind kind, NvAddressSpace* as); +Result nvBufferCreateRw(NvBuffer* m, size_t size, u32 align, NvKind kind, NvAddressSpace* as); void nvBufferFree(NvBuffer* m); void* nvBufferGetCpuAddr(NvBuffer* m); iova_t nvBufferGetGpuAddr(NvBuffer* m); -Result nvBufferMapAsTexture(NvBuffer* m, NvBufferKind kind); +Result nvBufferMapAsTexture(NvBuffer* m, NvKind kind); iova_t nvBufferGetGpuAddrTexture(NvBuffer* m); Result nvBufferMakeCpuUncached(NvBuffer* m); diff --git a/nx/include/switch/nvidia/channel.h b/nx/include/switch/nvidia/channel.h index d75a45d1..4b0fef07 100644 --- a/nx/include/switch/nvidia/channel.h +++ b/nx/include/switch/nvidia/channel.h @@ -1,5 +1,5 @@ #pragma once -#include "ioctl.h" +#include "types.h" typedef struct NvChannel { u32 fd; diff --git a/nx/include/switch/nvidia/info.h b/nx/include/switch/nvidia/info.h index 49705ffb..6c36519c 100644 --- a/nx/include/switch/nvidia/info.h +++ b/nx/include/switch/nvidia/info.h @@ -1,6 +1,7 @@ #pragma once +#include "types.h" -Result nvInfoInit(); -void nvInfoExit(); +Result nvInfoInit(void); +void nvInfoExit(void); -u32 nvInfoGetZcullCtxSize(); +u32 nvInfoGetZcullCtxSize(void); diff --git a/nx/include/switch/nvidia/ioctl.h b/nx/include/switch/nvidia/ioctl.h index ee090781..d9442c00 100644 --- a/nx/include/switch/nvidia/ioctl.h +++ b/nx/include/switch/nvidia/ioctl.h @@ -1,5 +1,5 @@ #pragma once -#include "../types.h" +#include "types.h" // The below defines are based on Linux kernel ioctl.h. #define _NV_IOC_NRBITS 8 @@ -185,5 +185,3 @@ Result nvioctlChannel_GetErrorNotification(u32 fd, NvError* out); Result nvioctlChannel_SetPriority(u32 fd, u32 priority); Result nvioctlChannel_AllocGpfifoEx2(u32 fd, u32 num_entries, u32 flags, u32 unk0, u32 unk1, u32 unk2, u32 unk3, nvioctl_fence *fence_out); Result nvioctlChannel_SetUserData(u32 fd, void* addr); - -typedef u64 iova_t; diff --git a/nx/include/switch/nvidia/types.h b/nx/include/switch/nvidia/types.h new file mode 100644 index 00000000..4ab28a94 --- /dev/null +++ b/nx/include/switch/nvidia/types.h @@ -0,0 +1,251 @@ +#pragma once +#include "../types.h" + +typedef u64 iova_t; + +typedef enum { + NvLayout_Pitch = 1, + NvLayout_Tiled = 2, + NvLayout_BlockLinear = 3, +} NvLayout; + +typedef enum { + NvDisplayScanFormat_Progressive = 0, + NvDisplayScanFormat_Interlaced = 1, +} NvDisplayScanFormat; + +typedef enum { + NvKind_Pitch = 0x0, + NvKind_Z16 = 0x1, + NvKind_Z16_2C = 0x2, + NvKind_Z16_MS2_2C = 0x3, + NvKind_Z16_MS4_2C = 0x4, + NvKind_Z16_MS8_2C = 0x5, + NvKind_Z16_MS16_2C = 0x6, + NvKind_Z16_2Z = 0x7, + NvKind_Z16_MS2_2Z = 0x8, + NvKind_Z16_MS4_2Z = 0x9, + NvKind_Z16_MS8_2Z = 0xa, + NvKind_Z16_MS16_2Z = 0xb, + NvKind_Z16_4CZ = 0xc, + NvKind_Z16_MS2_4CZ = 0xd, + NvKind_Z16_MS4_4CZ = 0xe, + NvKind_Z16_MS8_4CZ = 0xf, + NvKind_Z16_MS16_4CZ = 0x10, + NvKind_S8Z24 = 0x11, + NvKind_S8Z24_1Z = 0x12, + NvKind_S8Z24_MS2_1Z = 0x13, + NvKind_S8Z24_MS4_1Z = 0x14, + NvKind_S8Z24_MS8_1Z = 0x15, + NvKind_S8Z24_MS16_1Z = 0x16, + NvKind_S8Z24_2CZ = 0x17, + NvKind_S8Z24_MS2_2CZ = 0x18, + NvKind_S8Z24_MS4_2CZ = 0x19, + NvKind_S8Z24_MS8_2CZ = 0x1a, + NvKind_S8Z24_MS16_2CZ = 0x1b, + NvKind_S8Z24_2CS = 0x1C, + NvKind_S8Z24_MS2_2CS = 0x1d, + NvKind_S8Z24_MS4_2CS = 0x1e, + NvKind_S8Z24_MS8_2CS = 0x1f, + NvKind_S8Z24_MS16_2CS = 0x20, + NvKind_S8Z24_4CSZV = 0x21, + NvKind_S8Z24_MS2_4CSZV = 0x22, + NvKind_S8Z24_MS4_4CSZV = 0x23, + NvKind_S8Z24_MS8_4CSZV = 0x24, + NvKind_S8Z24_MS16_4CSZV = 0x25, + NvKind_V8Z24_MS4_VC12 = 0x26, + NvKind_V8Z24_MS4_VC4 = 0x27, + NvKind_V8Z24_MS8_VC8 = 0x28, + NvKind_V8Z24_MS8_VC24 = 0x29, + NvKind_S8 = 0x2a, + NvKind_S8_2S = 0x2b, + NvKind_V8Z24_MS4_VC12_1ZV = 0x2e, + NvKind_V8Z24_MS4_VC4_1ZV = 0x2f, + NvKind_V8Z24_MS8_VC8_1ZV = 0x30, + NvKind_V8Z24_MS8_VC24_1ZV = 0x31, + NvKind_V8Z24_MS4_VC12_2CS = 0x32, + NvKind_V8Z24_MS4_VC4_2CS = 0x33, + NvKind_V8Z24_MS8_VC8_2CS = 0x34, + NvKind_V8Z24_MS8_VC24_2CS = 0x35, + NvKind_V8Z24_MS4_VC12_2CZV = 0x3a, + NvKind_V8Z24_MS4_VC4_2CZV = 0x3b, + NvKind_V8Z24_MS8_VC8_2CZV = 0x3c, + NvKind_V8Z24_MS8_VC24_2CZV = 0x3d, + NvKind_V8Z24_MS4_VC12_2ZV = 0x3e, + NvKind_V8Z24_MS4_VC4_2ZV = 0x3f, + NvKind_V8Z24_MS8_VC8_2ZV = 0x40, + NvKind_V8Z24_MS8_VC24_2ZV = 0x41, + NvKind_V8Z24_MS4_VC12_4CSZV = 0x42, + NvKind_V8Z24_MS4_VC4_4CSZV = 0x43, + NvKind_V8Z24_MS8_VC8_4CSZV = 0x44, + NvKind_V8Z24_MS8_VC24_4CSZV = 0x45, + NvKind_Z24S8 = 0x46, + NvKind_Z24S8_1Z = 0x47, + NvKind_Z24S8_MS2_1Z = 0x48, + NvKind_Z24S8_MS4_1Z = 0x49, + NvKind_Z24S8_MS8_1Z = 0x4a, + NvKind_Z24S8_MS16_1Z = 0x4b, + NvKind_Z24S8_2CS = 0x4c, + NvKind_Z24S8_MS2_2CS = 0x4d, + NvKind_Z24S8_MS4_2CS = 0x4e, + NvKind_Z24S8_MS8_2CS = 0x4f, + NvKind_Z24S8_MS16_2CS = 0x50, + NvKind_Z24S8_2CZ = 0x51, + NvKind_Z24S8_MS2_2CZ = 0x52, + NvKind_Z24S8_MS4_2CZ = 0x53, + NvKind_Z24S8_MS8_2CZ = 0x54, + NvKind_Z24S8_MS16_2CZ = 0x55, + NvKind_Z24S8_4CSZV = 0x56, + NvKind_Z24S8_MS2_4CSZV = 0x57, + NvKind_Z24S8_MS4_4CSZV = 0x58, + NvKind_Z24S8_MS8_4CSZV = 0x59, + NvKind_Z24S8_MS16_4CSZV = 0x5a, + NvKind_Z24V8_MS4_VC12 = 0x5b, + NvKind_Z24V8_MS4_VC4 = 0x5C, + NvKind_Z24V8_MS8_VC8 = 0x5d, + NvKind_Z24V8_MS8_VC24 = 0x5e, + NvKind_Z24V8_MS4_VC12_1ZV = 0x63, + NvKind_Z24V8_MS4_VC4_1ZV = 0x64, + NvKind_Z24V8_MS8_VC8_1ZV = 0x65, + NvKind_Z24V8_MS8_VC24_1ZV = 0x66, + NvKind_Z24V8_MS4_VC12_2CS = 0x67, + NvKind_Z24V8_MS4_VC4_2CS = 0x68, + NvKind_Z24V8_MS8_VC8_2CS = 0x69, + NvKind_Z24V8_MS8_VC24_2CS = 0x6a, + NvKind_Z24V8_MS4_VC12_2CZV = 0x6f, + NvKind_Z24V8_MS4_VC4_2CZV = 0x70, + NvKind_Z24V8_MS8_VC8_2CZV = 0x71, + NvKind_Z24V8_MS8_VC24_2CZV = 0x72, + NvKind_Z24V8_MS4_VC12_2ZV = 0x73, + NvKind_Z24V8_MS4_VC4_2ZV = 0x74, + NvKind_Z24V8_MS8_VC8_2ZV = 0x75, + NvKind_Z24V8_MS8_VC24_2ZV = 0x76, + NvKind_Z24V8_MS4_VC12_4CSZV = 0x77, + NvKind_Z24V8_MS4_VC4_4CSZV = 0x78, + NvKind_Z24V8_MS8_VC8_4CSZV = 0x79, + NvKind_Z24V8_MS8_VC24_4CSZV = 0x7a, + NvKind_ZF32 = 0x7b, + NvKind_ZF32_1Z = 0x7C, + NvKind_ZF32_MS2_1Z = 0x7d, + NvKind_ZF32_MS4_1Z = 0x7e, + NvKind_ZF32_MS8_1Z = 0x7f, + NvKind_ZF32_MS16_1Z = 0x80, + NvKind_ZF32_2CS = 0x81, + NvKind_ZF32_MS2_2CS = 0x82, + NvKind_ZF32_MS4_2CS = 0x83, + NvKind_ZF32_MS8_2CS = 0x84, + NvKind_ZF32_MS16_2CS = 0x85, + NvKind_ZF32_2CZ = 0x86, + NvKind_ZF32_MS2_2CZ = 0x87, + NvKind_ZF32_MS4_2CZ = 0x88, + NvKind_ZF32_MS8_2CZ = 0x89, + NvKind_ZF32_MS16_2CZ = 0x8a, + NvKind_X8Z24_X16V8S8_MS4_VC12 = 0x8b, + NvKind_X8Z24_X16V8S8_MS4_VC4 = 0x8c, + NvKind_X8Z24_X16V8S8_MS8_VC8 = 0x8d, + NvKind_X8Z24_X16V8S8_MS8_VC24 = 0x8e, + NvKind_X8Z24_X16V8S8_MS4_VC12_1CS = 0x8f, + NvKind_X8Z24_X16V8S8_MS4_VC4_1CS = 0x90, + NvKind_X8Z24_X16V8S8_MS8_VC8_1CS = 0x91, + NvKind_X8Z24_X16V8S8_MS8_VC24_1CS = 0x92, + NvKind_X8Z24_X16V8S8_MS4_VC12_1ZV = 0x97, + NvKind_X8Z24_X16V8S8_MS4_VC4_1ZV = 0x98, + NvKind_X8Z24_X16V8S8_MS8_VC8_1ZV = 0x99, + NvKind_X8Z24_X16V8S8_MS8_VC24_1ZV = 0x9a, + NvKind_X8Z24_X16V8S8_MS4_VC12_1CZV = 0x9b, + NvKind_X8Z24_X16V8S8_MS4_VC4_1CZV = 0x9c, + NvKind_X8Z24_X16V8S8_MS8_VC8_1CZV = 0x9d, + NvKind_X8Z24_X16V8S8_MS8_VC24_1CZV = 0x9e, + NvKind_X8Z24_X16V8S8_MS4_VC12_2CS = 0x9f, + NvKind_X8Z24_X16V8S8_MS4_VC4_2CS = 0xa0, + NvKind_X8Z24_X16V8S8_MS8_VC8_2CS = 0xa1, + NvKind_X8Z24_X16V8S8_MS8_VC24_2CS = 0xa2, + NvKind_X8Z24_X16V8S8_MS4_VC12_2CSZV = 0xa3, + NvKind_X8Z24_X16V8S8_MS4_VC4_2CSZV = 0xa4, + NvKind_X8Z24_X16V8S8_MS8_VC8_2CSZV = 0xa5, + NvKind_X8Z24_X16V8S8_MS8_VC24_2CSZV = 0xa6, + NvKind_ZF32_X16V8S8_MS4_VC12 = 0xa7, + NvKind_ZF32_X16V8S8_MS4_VC4 = 0xa8, + NvKind_ZF32_X16V8S8_MS8_VC8 = 0xa9, + NvKind_ZF32_X16V8S8_MS8_VC24 = 0xaa, + NvKind_ZF32_X16V8S8_MS4_VC12_1CS = 0xab, + NvKind_ZF32_X16V8S8_MS4_VC4_1CS = 0xac, + NvKind_ZF32_X16V8S8_MS8_VC8_1CS = 0xad, + NvKind_ZF32_X16V8S8_MS8_VC24_1CS = 0xae, + NvKind_ZF32_X16V8S8_MS4_VC12_1ZV = 0xb3, + NvKind_ZF32_X16V8S8_MS4_VC4_1ZV = 0xb4, + NvKind_ZF32_X16V8S8_MS8_VC8_1ZV = 0xb5, + NvKind_ZF32_X16V8S8_MS8_VC24_1ZV = 0xb6, + NvKind_ZF32_X16V8S8_MS4_VC12_1CZV = 0xb7, + NvKind_ZF32_X16V8S8_MS4_VC4_1CZV = 0xb8, + NvKind_ZF32_X16V8S8_MS8_VC8_1CZV = 0xb9, + NvKind_ZF32_X16V8S8_MS8_VC24_1CZV = 0xba, + NvKind_ZF32_X16V8S8_MS4_VC12_2CS = 0xbb, + NvKind_ZF32_X16V8S8_MS4_VC4_2CS = 0xbc, + NvKind_ZF32_X16V8S8_MS8_VC8_2CS = 0xbd, + NvKind_ZF32_X16V8S8_MS8_VC24_2CS = 0xbe, + NvKind_ZF32_X16V8S8_MS4_VC12_2CSZV = 0xbf, + NvKind_ZF32_X16V8S8_MS4_VC4_2CSZV = 0xc0, + NvKind_ZF32_X16V8S8_MS8_VC8_2CSZV = 0xc1, + NvKind_ZF32_X16V8S8_MS8_VC24_2CSZV = 0xc2, + NvKind_ZF32_X24S8 = 0xc3, + NvKind_ZF32_X24S8_1CS = 0xc4, + NvKind_ZF32_X24S8_MS2_1CS = 0xc5, + NvKind_ZF32_X24S8_MS4_1CS = 0xc6, + NvKind_ZF32_X24S8_MS8_1CS = 0xc7, + NvKind_ZF32_X24S8_MS16_1CS = 0xc8, + NvKind_SmskedMessage = 0xca, + NvKind_SmhostMessage = 0xcb, + NvKind_C64_MS2_2CRA = 0xcd, + NvKind_ZF32_X24S8_2CSZV = 0xce, + NvKind_ZF32_X24S8_MS2_2CSZV = 0xcf, + NvKind_ZF32_X24S8_MS4_2CSZV = 0xd0, + NvKind_ZF32_X24S8_MS8_2CSZV = 0xd1, + NvKind_ZF32_X24S8_MS16_2CSZV = 0xd2, + NvKind_ZF32_X24S8_2CS = 0xd3, + NvKind_ZF32_X24S8_MS2_2CS = 0xd4, + NvKind_ZF32_X24S8_MS4_2CS = 0xd5, + NvKind_ZF32_X24S8_MS8_2CS = 0xd6, + NvKind_ZF32_X24S8_MS16_2CS = 0xd7, + NvKind_C32_2C = 0xd8, + NvKind_C32_2CBR = 0xd9, + NvKind_C32_2CBA = 0xda, + NvKind_C32_2CRA = 0xdb, + NvKind_C32_2BRA = 0xdc, + NvKind_C32_MS2_2C = 0xdd, + NvKind_C32_MS2_2CBR = 0xde, + NvKind_C32_MS2_2CRA = 0xcc, + NvKind_C32_MS4_2C = 0xdf, + NvKind_C32_MS4_2CBR = 0xe0, + NvKind_C32_MS4_2CBA = 0xe1, + NvKind_C32_MS4_2CRA = 0xe2, + NvKind_C32_MS4_2BRA = 0xe3, + NvKind_C32_MS8_MS16_2C = 0xe4, + NvKind_C32_MS8_MS16_2CRA = 0xe5, + NvKind_C64_2C = 0xe6, + NvKind_C64_2CBR = 0xe7, + NvKind_C64_2CBA = 0xe8, + NvKind_C64_2CRA = 0xe9, + NvKind_C64_2BRA = 0xea, + NvKind_C64_MS2_2C = 0xeb, + NvKind_C64_MS2_2CBR = 0xec, + NvKind_C64_MS4_2C = 0xed, + NvKind_C64_MS4_2CBR = 0xee, + NvKind_C64_MS4_2CBA = 0xef, + NvKind_C64_MS4_2CRA = 0xf0, + NvKind_C64_MS4_2BRA = 0xf1, + NvKind_C64_MS8_MS16_2C = 0xf2, + NvKind_C64_MS8_MS16_2CRA = 0xf3, + NvKind_C128_2C = 0xf4, + NvKind_C128_2CR = 0xf5, + NvKind_C128_MS2_2C = 0xf6, + NvKind_C128_MS2_2CR = 0xf7, + NvKind_C128_MS4_2C = 0xf8, + NvKind_C128_MS4_2CR = 0xf9, + NvKind_C128_MS8_MS16_2C = 0xfa, + NvKind_C128_MS8_MS16_2CR = 0xfb, + NvKind_X8C24 = 0xfc, + NvKind_PitchNoSwizzle = 0xfd, + NvKind_Generic_16BX2 = 0xfe, + NvKind_Invalid = 0xff, +} NvKind; diff --git a/nx/source/nvidia/address_space.c b/nx/source/nvidia/address_space.c index dcc85b96..1efdb405 100644 --- a/nx/source/nvidia/address_space.c +++ b/nx/source/nvidia/address_space.c @@ -56,7 +56,7 @@ Result nvAddressSpaceReserveFull(NvAddressSpace* a) { } Result nvAddressSpaceMapBuffer( - NvAddressSpace* a, u32 fd, NvBufferKind kind, + NvAddressSpace* a, u32 fd, NvKind kind, iova_t* iova_out) { return nvioctlNvhostAsGpu_MapBufferEx( a->fd, NvMapBufferFlags_IsCachable, kind, fd, 0x10000, 0, 0, 0, iova_out); diff --git a/nx/source/nvidia/buffer.c b/nx/source/nvidia/buffer.c index d738dc52..00d88a55 100644 --- a/nx/source/nvidia/buffer.c +++ b/nx/source/nvidia/buffer.c @@ -42,7 +42,7 @@ u32 nvBufferGetNvmapFd(void) { } static Result _nvBufferCreate( - NvBuffer* m, size_t size, u32 flags, u32 align, NvBufferKind kind, + NvBuffer* m, size_t size, u32 flags, u32 align, NvKind kind, NvAddressSpace* as) { Result rc; @@ -80,12 +80,12 @@ static Result _nvBufferCreate( } Result nvBufferCreate( - NvBuffer* m, size_t size, u32 align, NvBufferKind kind, NvAddressSpace* as) { + NvBuffer* m, size_t size, u32 align, NvKind kind, NvAddressSpace* as) { return _nvBufferCreate(m, size, 0, align, kind, as); } Result nvBufferCreateRw( - NvBuffer* m, size_t size, u32 align, NvBufferKind kind, NvAddressSpace* as) { + NvBuffer* m, size_t size, u32 align, NvKind kind, NvAddressSpace* as) { return _nvBufferCreate(m, size, NvBufferFlags_Writable, align, kind, as); } @@ -123,7 +123,7 @@ iova_t nvBufferGetGpuAddr(NvBuffer* m) { return m->gpu_addr; } -Result nvBufferMapAsTexture(NvBuffer* m, NvBufferKind kind) { +Result nvBufferMapAsTexture(NvBuffer* m, NvKind kind) { return nvAddressSpaceMapBuffer(m->addr_space, m->fd, kind, &m->gpu_addr_texture); } diff --git a/nx/source/nvidia/gpu/cmd_list.c b/nx/source/nvidia/gpu/cmd_list.c index 3d5cc281..811c55b1 100644 --- a/nx/source/nvidia/gpu/cmd_list.c +++ b/nx/source/nvidia/gpu/cmd_list.c @@ -22,7 +22,7 @@ Result nvCmdListCreate(NvCmdList* c, NvGpu* parent, size_t max_cmds) Result rc; rc = nvBufferCreate( - &c->buffer, max_cmds * 4, 0x1000, NvBufferKind_Pitch, + &c->buffer, max_cmds * 4, 0x1000, NvKind_Pitch, &parent->addr_space); if (R_SUCCEEDED(rc)) { diff --git a/nx/source/nvidia/gpu/zcull_ctx.c b/nx/source/nvidia/gpu/zcull_ctx.c index a26e9ede..cbe9e603 100644 --- a/nx/source/nvidia/gpu/zcull_ctx.c +++ b/nx/source/nvidia/gpu/zcull_ctx.c @@ -25,11 +25,11 @@ Result nvZcullContextCreate(NvZcullContext* z, NvGpu* parent) z->parent = parent; rc = nvBufferCreateRw( - &z->ctx_buf, nvInfoGetZcullCtxSize(), 0x20000, NvBufferKind_Pitch, + &z->ctx_buf, nvInfoGetZcullCtxSize(), 0x20000, NvKind_Pitch, &parent->addr_space); if (R_SUCCEEDED(rc)) - rc = nvBufferMapAsTexture(&z->ctx_buf, NvBufferKind_Generic_16BX2); + rc = nvBufferMapAsTexture(&z->ctx_buf, NvKind_Generic_16BX2); if (R_SUCCEEDED(rc)) rc = nvioctlChannel_ZCullBind(