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kernel_ldr::cpu: prevent reordering around barrier instructions

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This commit is contained in:
Michael Scire 2019-12-17 07:07:35 -08:00
parent fcae4af5f7
commit 4e81f0176a
1 changed files with 4 additions and 4 deletions
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8
libmesosphere/include/mesosphere/arch/arm64/kern_cpu.hpp
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@ -21,19 +21,19 @@ namespace ams::kern::arm64::cpu {
/* Helpers for managing memory state. */
ALWAYS_INLINE void DataSynchronizationBarrier() {
__asm__ __volatile__("dsb sy");
__asm__ __volatile__("dsb sy" ::: "memory");
}
ALWAYS_INLINE void DataSynchronizationBarrierInnerShareable() {
__asm__ __volatile__("dsb ish");
__asm__ __volatile__("dsb ish" ::: "memory");
}
ALWAYS_INLINE void DataMemoryBarrier() {
__asm__ __volatile__("dmb sy");
__asm__ __volatile__("dmb sy" ::: "memory");
}
ALWAYS_INLINE void InstructionMemoryBarrier() {
__asm__ __volatile__("isb");
__asm__ __volatile__("isb" ::: "memory");
}
ALWAYS_INLINE void EnsureInstructionConsistency() {