From 4e81f0176a8d044a4f308868748eee673cfee65c Mon Sep 17 00:00:00 2001 From: Michael Scire Date: Tue, 17 Dec 2019 07:07:35 -0800 Subject: [PATCH] kernel_ldr::cpu: prevent reordering around barrier instructions --- libmesosphere/include/mesosphere/arch/arm64/kern_cpu.hpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/libmesosphere/include/mesosphere/arch/arm64/kern_cpu.hpp b/libmesosphere/include/mesosphere/arch/arm64/kern_cpu.hpp index 4a674cd3..eff9bf84 100644 --- a/libmesosphere/include/mesosphere/arch/arm64/kern_cpu.hpp +++ b/libmesosphere/include/mesosphere/arch/arm64/kern_cpu.hpp @@ -21,19 +21,19 @@ namespace ams::kern::arm64::cpu { /* Helpers for managing memory state. */ ALWAYS_INLINE void DataSynchronizationBarrier() { - __asm__ __volatile__("dsb sy"); + __asm__ __volatile__("dsb sy" ::: "memory"); } ALWAYS_INLINE void DataSynchronizationBarrierInnerShareable() { - __asm__ __volatile__("dsb ish"); + __asm__ __volatile__("dsb ish" ::: "memory"); } ALWAYS_INLINE void DataMemoryBarrier() { - __asm__ __volatile__("dmb sy"); + __asm__ __volatile__("dmb sy" ::: "memory"); } ALWAYS_INLINE void InstructionMemoryBarrier() { - __asm__ __volatile__("isb"); + __asm__ __volatile__("isb" ::: "memory"); } ALWAYS_INLINE void EnsureInstructionConsistency() {