mirror of
https://github.com/switchbrew/libnx.git
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296 lines
11 KiB
C
296 lines
11 KiB
C
#pragma once
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#include "types.h"
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// The below defines are based on Linux kernel ioctl.h.
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#define _NV_IOC_NRBITS 8
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#define _NV_IOC_TYPEBITS 8
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#define _NV_IOC_SIZEBITS 14
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#define _NV_IOC_DIRBITS 2
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#define _NV_IOC_NRMASK ((1 << _NV_IOC_NRBITS)-1)
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#define _NV_IOC_TYPEMASK ((1 << _NV_IOC_TYPEBITS)-1)
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#define _NV_IOC_SIZEMASK ((1 << _NV_IOC_SIZEBITS)-1)
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#define _NV_IOC_DIRMASK ((1 << _NV_IOC_DIRBITS)-1)
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#define _NV_IOC_NRSHIFT 0
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#define _NV_IOC_TYPESHIFT (_NV_IOC_NRSHIFT+_NV_IOC_NRBITS)
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#define _NV_IOC_SIZESHIFT (_NV_IOC_TYPESHIFT+_NV_IOC_TYPEBITS)
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#define _NV_IOC_DIRSHIFT (_NV_IOC_SIZESHIFT+_NV_IOC_SIZEBITS)
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// Direction bits.
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#define _NV_IOC_NONE 0U
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#define _NV_IOC_WRITE 1U
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#define _NV_IOC_READ 2U
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#define _NV_IOC(dir,type,nr,size) \
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(((dir) << _NV_IOC_DIRSHIFT) | \
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((type) << _NV_IOC_TYPESHIFT) | \
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((nr) << _NV_IOC_NRSHIFT) | \
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((size) << _NV_IOC_SIZESHIFT))
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/* used to create numbers */
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#define _NV_IO(type,nr) _NV_IOC(_NV_IOC_NONE,(type),(nr),0)
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#define _NV_IOR(type,nr,size) _NV_IOC(_NV_IOC_READ,(type),(nr),sizeof(size))
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#define _NV_IOW(type,nr,size) _NV_IOC(_NV_IOC_WRITE,(type),(nr),sizeof(size))
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#define _NV_IOWR(type,nr,size) _NV_IOC(_NV_IOC_READ|_NV_IOC_WRITE,(type),(nr),sizeof(size))
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/* used to decode ioctl numbers.. */
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#define _NV_IOC_DIR(nr) (((nr) >> _NV_IOC_DIRSHIFT) & _NV_IOC_DIRMASK)
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#define _NV_IOC_TYPE(nr) (((nr) >> _NV_IOC_TYPESHIFT) & _NV_IOC_TYPEMASK)
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#define _NV_IOC_NR(nr) (((nr) >> _NV_IOC_NRSHIFT) & _NV_IOC_NRMASK)
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#define _NV_IOC_SIZE(nr) (((nr) >> _NV_IOC_SIZESHIFT) & _NV_IOC_SIZEMASK)
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#define __nv_in
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#define __nv_out
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#define __nv_inout
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typedef struct {
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u32 width_align_pixels; // 0x20 (32)
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u32 height_align_pixels; // 0x20 (32)
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u32 pixel_squares_by_aliquots; // 0x400 (1024)
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u32 aliquot_total; // 0x800 (2048)
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u32 region_byte_multiplier; // 0x20 (32)
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u32 region_header_size; // 0x20 (32)
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u32 subregion_header_size; // 0xC0 (192)
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u32 subregion_width_align_pixels; // 0x20 (32)
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u32 subregion_height_align_pixels; // 0x40 (64)
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u32 subregion_count; // 0x10 (16)
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} nvioctl_zcull_info;
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typedef struct {
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u32 color_ds[4];
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u32 color_l2[4];
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u32 depth;
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u32 ref_cnt;
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u32 format;
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u32 type;
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u32 size;
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} nvioctl_zbc_entry;
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typedef struct {
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u32 arch; // 0x120 (NVGPU_GPU_ARCH_GM200)
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u32 impl; // 0xB (NVGPU_GPU_IMPL_GM20B)
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u32 rev; // 0xA1 (Revision A1)
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u32 num_gpc; // 0x1
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u64 L2_cache_size; // 0x40000
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u64 on_board_video_memory_size; // 0x0 (not used)
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u32 num_tpc_per_gpc; // 0x2
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u32 bus_type; // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
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u32 big_page_size; // 0x20000
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u32 compression_page_size; // 0x20000
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u32 pde_coverage_bit_count; // 0x1B
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u32 available_big_page_sizes; // 0x30000
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u32 gpc_mask; // 0x1
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u32 sm_arch_sm_version; // 0x503 (Maxwell Generation 5.0.3?)
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u32 sm_arch_spa_version; // 0x503 (Maxwell Generation 5.0.3?)
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u32 sm_arch_warp_count; // 0x80
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u32 gpu_va_bit_count; // 0x28
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u32 reserved; // NULL
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u64 flags; // 0x55
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u32 twod_class; // 0x902D (FERMI_TWOD_A)
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u32 threed_class; // 0xB197 (MAXWELL_B)
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u32 compute_class; // 0xB1C0 (MAXWELL_COMPUTE_B)
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u32 gpfifo_class; // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)
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u32 inline_to_memory_class; // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
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u32 dma_copy_class; // 0xB0B5 (MAXWELL_DMA_COPY_A)
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u32 max_fbps_count; // 0x1
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u32 fbp_en_mask; // 0x0 (disabled)
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u32 max_ltc_per_fbp; // 0x2
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u32 max_lts_per_ltc; // 0x1
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u32 max_tex_per_tpc; // 0x0 (not supported)
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u32 max_gpc_count; // 0x1
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u32 rop_l2_en_mask_0; // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)
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u32 rop_l2_en_mask_1; // 0x0
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u64 chipname; // 0x6230326D67 ("gm20b")
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u64 gr_compbit_store_base_hw; // 0x0 (not supported)
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} nvioctl_gpu_characteristics;
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typedef struct {
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u64 offset;
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u32 page_size;
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u32 pad;
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u64 pages;
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} nvioctl_va_region;
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typedef struct {
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u32 slot; // always 0x07 (?)
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u32 mask;
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} nvioctl_zbc_slot_mask;
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typedef struct {
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u64 timestamp;
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u64 reserved;
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} nvioctl_gpu_time;
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typedef struct {
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u32 id;
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u32 value;
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} nvioctl_fence;
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typedef struct {
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union {
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u64 desc;
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u32 desc32[2];
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};
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} nvioctl_gpfifo_entry;
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typedef struct {
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u32 mem;
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u32 offset;
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u32 words;
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} nvioctl_cmdbuf;
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typedef struct {
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u32 cmdbuf_mem;
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u32 cmdbuf_offset;
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u32 target;
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u32 target_offset;
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} nvioctl_reloc;
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typedef struct {
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u32 shift;
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} nvioctl_reloc_shift;
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typedef struct {
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u32 syncpt_id;
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u32 syncpt_incrs;
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} nvioctl_syncpt_incr;
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typedef struct {
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u32 handle;
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u32 iova;
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} nvioctl_command_buffer_map;
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typedef struct {
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uint32_t rate;
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uint32_t moduleid;
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} nvioctl_clk_rate;
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#define NVGPU_ZBC_TYPE_INVALID 0
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#define NVGPU_ZBC_TYPE_COLOR 1
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#define NVGPU_ZBC_TYPE_DEPTH 2
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// Used with nvioctlNvmap_Param().
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typedef enum nvioctl_map_param {
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NvMapParam_Size = 1,
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NvMapParam_Alignment = 2,
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NvMapParam_Base = 3,
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NvMapParam_Heap = 4,
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NvMapParam_Kind = 5
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} NvMapParam;
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// Used with nvioctlChannel_AllocObjCtx().
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typedef enum nvioctl_channel_obj_classnum {
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NvClassNumber_2D = 0x902D,
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NvClassNumber_3D = 0xB197,
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NvClassNumber_Compute = 0xB1C0,
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NvClassNumber_Kepler = 0xA140,
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NvClassNumber_DMA = 0xB0B5,
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NvClassNumber_ChannelGpfifo = 0xB06F
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} NvClassNumber;
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// Used with nvioctlChannel_SetPriority().
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typedef enum nvioctl_channel_priority {
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NvChannelPriority_Low = 50,
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NvChannelPriority_Medium = 100,
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NvChannelPriority_High = 150
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} NvChannelPriority;
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// Used with nvioctlChannel_ZCullBind().
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typedef enum {
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NvZcullConfig_Global = 0,
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NvZcullConfig_NoCtxSwitch = 1,
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NvZcullConfig_SeparateBuffer = 2,
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NvZcullConfig_PartOfRegularBuffer = 3
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} NvZcullConfig;
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// Used with nvioctlNvhostAsGpu_AllocSpace().
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typedef enum {
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NvAllocSpaceFlags_FixedOffset = 1,
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NvAllocSpaceFlags_Sparse = 2,
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} NvAllocSpaceFlags;
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// Used with nvioctlNvhostAsGpu_MapBufferEx().
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typedef enum {
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NvMapBufferFlags_FixedOffset = 1,
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NvMapBufferFlags_IsCacheable = 4,
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NvMapBufferFlags_Modify = 0x100,
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} NvMapBufferFlags;
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typedef enum {
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NvNotificationType_FifoErrorIdleTimeout=8,
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NvNotificationType_GrErrorSwNotify=13,
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NvNotificationType_GrSemaphoreTimeout=24,
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NvNotificationType_GrIllegalNotify=25,
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NvNotificationType_FifoErrorMmuErrFlt=31,
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NvNotificationType_PbdmaError=32,
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NvNotificationType_ResetChannelVerifError=43,
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NvNotificationType_PbdmaPushbufferCrcMismatch=80
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} NvNotificationType;
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typedef struct {
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u64 timestamp;
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u32 info32; // see NvNotificationType
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u16 info16;
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u16 status; // always -1
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} NvNotification;
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typedef struct {
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u32 type;
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u32 info[31];
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} NvError;
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Result nvioctlNvhostCtrl_SyncptRead(u32 fd, u32 id, u32* out);
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Result nvioctlNvhostCtrl_SyncptIncr(u32 fd, u32 id);
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Result nvioctlNvhostCtrl_SyncptWait(u32 fd, u32 id, u32 threshold, u32 timeout);
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Result nvioctlNvhostCtrl_EventSignal(u32 fd, u32 event_id);
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Result nvioctlNvhostCtrl_EventWait(u32 fd, u32 syncpt_id, u32 threshold, s32 timeout, u32 event_id, u32 *out);
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Result nvioctlNvhostCtrl_EventWaitAsync(u32 fd, u32 syncpt_id, u32 threshold, s32 timeout, u32 event_id);
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Result nvioctlNvhostCtrl_EventRegister(u32 fd, u32 event_id);
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Result nvioctlNvhostCtrl_EventUnregister(u32 fd, u32 event_id);
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Result nvioctlNvhostCtrlGpu_ZCullGetCtxSize(u32 fd, u32 *out);
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Result nvioctlNvhostCtrlGpu_ZCullGetInfo(u32 fd, nvioctl_zcull_info *out);
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Result nvioctlNvhostCtrlGpu_ZbcSetTable(u32 fd, const u32 color_ds[4], const u32 color_l2[4], u32 depth, u32 format, u32 type);
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Result nvioctlNvhostCtrlGpu_ZbcQueryTable(u32 fd, u32 index, nvioctl_zbc_entry *out);
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Result nvioctlNvhostCtrlGpu_GetCharacteristics(u32 fd, nvioctl_gpu_characteristics *out);
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Result nvioctlNvhostCtrlGpu_GetTpcMasks(u32 fd, void *buffer, size_t size);
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Result nvioctlNvhostCtrlGpu_ZbcGetActiveSlotMask(u32 fd, nvioctl_zbc_slot_mask *out);
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Result nvioctlNvhostCtrlGpu_GetGpuTime(u32 fd, nvioctl_gpu_time *out);
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Result nvioctlNvhostAsGpu_BindChannel(u32 fd, u32 channel_fd);
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Result nvioctlNvhostAsGpu_AllocSpace(u32 fd, u32 pages, u32 page_size, u32 flags, u64 align_or_offset, u64 *offset);
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Result nvioctlNvhostAsGpu_FreeSpace(u32 fd, u64 offset, u32 pages, u32 page_size);
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Result nvioctlNvhostAsGpu_MapBufferEx(u32 fd, u32 flags, u32 kind, u32 nvmap_handle, u32 page_size, u64 buffer_offset, u64 mapping_size, u64 input_offset, u64 *offset);
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Result nvioctlNvhostAsGpu_UnmapBuffer(u32 fd, u64 offset);
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Result nvioctlNvhostAsGpu_GetVARegions(u32 fd, nvioctl_va_region regions[2]);
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Result nvioctlNvhostAsGpu_InitializeEx(u32 fd, u32 flags, u32 big_page_size);
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Result nvioctlNvmap_Create(u32 fd, u32 size, u32 *nvmap_handle);
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Result nvioctlNvmap_FromId(u32 fd, u32 id, u32 *nvmap_handle);
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Result nvioctlNvmap_Alloc(u32 fd, u32 nvmap_handle, u32 heapmask, u32 flags, u32 align, u8 kind, void* addr);
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Result nvioctlNvmap_Free(u32 fd, u32 nvmap_handle);
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Result nvioctlNvmap_Param(u32 fd, u32 nvmap_handle, NvMapParam param, u32 *result);
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Result nvioctlNvmap_GetId(u32 fd, u32 nvmap_handle, u32 *id);
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Result nvioctlChannel_SetNvmapFd(u32 fd, u32 nvmap_fd);
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Result nvioctlChannel_SubmitGpfifo(u32 fd, nvioctl_gpfifo_entry *entries, u32 num_entries, u32 flags, nvioctl_fence *fence_inout);
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Result nvioctlChannel_KickoffPb(u32 fd, nvioctl_gpfifo_entry *entries, u32 num_entries, u32 flags, nvioctl_fence *fence_inout);
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Result nvioctlChannel_AllocObjCtx(u32 fd, u32 class_num, u32 flags, u64* id_out);
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Result nvioctlChannel_ZCullBind(u32 fd, u64 gpu_va, u32 mode);
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Result nvioctlChannel_SetErrorNotifier(u32 fd, u32 enable);
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Result nvioctlChannel_GetErrorInfo(u32 fd, NvError* out);
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Result nvioctlChannel_GetErrorNotification(u32 fd, NvNotification* out);
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Result nvioctlChannel_SetPriority(u32 fd, u32 priority);
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Result nvioctlChannel_SetTimeout(u32 fd, u32 timeout);
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Result nvioctlChannel_AllocGpfifoEx2(u32 fd, u32 num_entries, u32 flags, u32 unk0, u32 unk1, u32 unk2, u32 unk3, nvioctl_fence *fence_out);
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Result nvioctlChannel_SetUserData(u32 fd, void* addr);
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Result nvioctlChannel_Submit(u32 fd, const nvioctl_cmdbuf *cmdbufs, u32 num_cmdbufs, const nvioctl_reloc *relocs, const nvioctl_reloc_shift *reloc_shifts, u32 num_relocs,
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const nvioctl_syncpt_incr *syncpt_incrs, u32 num_syncpt_incrs, nvioctl_fence *fences, u32 num_fences);
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Result nvioctlChannel_GetSyncpt(u32 fd, u32 module_id, u32 *syncpt);
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Result nvioctlChannel_GetModuleClockRate(u32 fd, u32 module_id, u32 *freq);
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Result nvioctlChannel_SetModuleClockRate(u32 fd, u32 module_id, u32 freq);
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Result nvioctlChannel_MapCommandBuffer(u32 fd, nvioctl_command_buffer_map *maps, u32 num_maps, bool compressed);
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Result nvioctlChannel_UnmapCommandBuffer(u32 fd, const nvioctl_command_buffer_map *maps, u32 num_maps, bool compressed);
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Result nvioctlChannel_SetSubmitTimeout(u32 fd, u32 timeout);
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