mirror of
https://github.com/switchbrew/libnx.git
synced 2025-06-21 20:42:44 +02:00
b577367011
Added PARCEL_LOGGING define in parcel.c. Fixed the 'code' value used in gfxproducerQueueBuffer(). Moved some gfxproducer init into nvgfx. Moved some nvgfx event init into nvgfxEventInit(). Updated the code using gfxproducerBufferInit() for setting the nvmap-handles. Disabled a nvQueryEvent() call which now fails. Other changes. The setup framebuf/windowbuf is now displayed.
108 lines
4.9 KiB
C
108 lines
4.9 KiB
C
typedef struct {
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u32 arch; // 0x120 (NVGPU_GPU_ARCH_GM200)
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u32 impl; // 0xB (NVGPU_GPU_IMPL_GM20B)
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u32 rev; // 0xA1 (Revision A1)
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u32 num_gpc; // 0x1
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u64 L2_cache_size; // 0x40000
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u64 on_board_video_memory_size; // 0x0 (not used)
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u32 num_tpc_per_gpc; // 0x2
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u32 bus_type; // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
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u32 big_page_size; // 0x20000
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u32 compression_page_size; // 0x20000
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u32 pde_coverage_bit_count; // 0x1B
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u32 available_big_page_sizes; // 0x30000
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u32 gpc_mask; // 0x1
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u32 sm_arch_sm_version; // 0x503 (Maxwell Generation 5.0.3?)
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u32 sm_arch_spa_version; // 0x503 (Maxwell Generation 5.0.3?)
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u32 sm_arch_warp_count; // 0x80
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u32 gpu_va_bit_count; // 0x28
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u32 reserved; // NULL
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u64 flags; // 0x55
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u32 twod_class; // 0x902D (FERMI_TWOD_A)
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u32 threed_class; // 0xB197 (MAXWELL_B)
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u32 compute_class; // 0xB1C0 (MAXWELL_COMPUTE_B)
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u32 gpfifo_class; // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)
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u32 inline_to_memory_class; // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
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u32 dma_copy_class; // 0xB0B5 (MAXWELL_DMA_COPY_A)
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u32 max_fbps_count; // 0x1
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u32 fbp_en_mask; // 0x0 (disabled)
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u32 max_ltc_per_fbp; // 0x2
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u32 max_lts_per_ltc; // 0x1
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u32 max_tex_per_tpc; // 0x0 (not supported)
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u32 max_gpc_count; // 0x1
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u32 rop_l2_en_mask_0; // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)
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u32 rop_l2_en_mask_1; // 0x0
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u64 chipname; // 0x6230326D67 ("gm20b")
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u64 gr_compbit_store_base_hw; // 0x0 (not supported)
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} gpu_characteristics;
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typedef struct {
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u64 offset;
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u32 page_size;
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u32 pad;
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u64 pages;
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} nvioctl_va_region;
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typedef struct {
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u32 mask; // always 0x07
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u32 flush; // active flush bit field
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} nvioctl_l2_state;
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typedef struct {
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u32 id;
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u32 value;
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} nvioctl_fence;
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typedef struct {
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u32 entry0;
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u32 entry1;
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} nvioctl_gpfifo_entry;
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//Used with nvioctlChannel_AllocObjCtx().
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enum nvioctl_channel_obj_classnum {
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NVIOCTL_CHANNEL_OBJ_CLASSNUM_2d = 0x902D,
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NVIOCTL_CHANNEL_OBJ_CLASSNUM_3d = 0xB197,
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NVIOCTL_CHANNEL_OBJ_CLASSNUM_compute = 0xB1C0,
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NVIOCTL_CHANNEL_OBJ_CLASSNUM_kepler = 0xA140,
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NVIOCTL_CHANNEL_OBJ_CLASSNUM_DMA = 0xB0B5,
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NVIOCTL_CHANNEL_OBJ_CLASSNUM_channel_gpfifo = 0xB06F
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};
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//Used with nvioctlChannel_SetPriority().
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enum nvioctl_channel_priority {
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NVIOCTL_CHANNEL_PRIORITY_low = 0x32,
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NVIOCTL_CHANNEL_PRIORITY_medium = 0x64,
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NVIOCTL_CHANNEL_PRIORITY_high = 0x96
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};
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Result nvioctlNvhostCtrl_EventSignal(u32 fd, u32 event_id);
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Result nvioctlNvhostCtrl_EventWait(u32 fd, u32 unk0, u32 unk1, s32 timeout, u32 event_id, u32 *out);
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Result nvioctlNvhostCtrl_EventRegister(u32 fd, u32 event_id);
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Result nvioctlNvhostCtrlGpu_ZCullGetCtxSize(u32 fd, u32 *out);
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Result nvioctlNvhostCtrlGpu_ZCullGetInfo(u32 fd, u32 out[40>>2]);
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Result nvioctlNvhostCtrlGpu_GetCharacteristics(u32 fd, gpu_characteristics *out);
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Result nvioctlNvhostCtrlGpu_GetTpcMasks(u32 fd, u32 inval, u32 out[24>>2]);
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Result nvioctlNvhostCtrlGpu_GetL2State(u32 fd, nvioctl_l2_state *out);
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Result nvioctlNvhostAsGpu_BindChannel(u32 fd, u32 channel_fd);
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Result nvioctlNvhostAsGpu_AllocSpace(u32 fd, u32 pages, u32 page_size, u32 flags, u64 align, u64 *offset);
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Result nvioctlNvhostAsGpu_MapBufferEx(u32 fd, u32 flags, u32 kind, u32 nvmap_handle, u32 page_size, u64 buffer_offset, u64 mapping_size, u64 input_offset, u64 *offset);
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Result nvioctlNvhostAsGpu_GetVARegions(u32 fd, nvioctl_va_region regions[2]);
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Result nvioctlNvhostAsGpu_InitializeEx(u32 fd, u32 big_page_size);
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Result nvioctlNvmap_Create(u32 fd, u32 size, u32 *nvmap_handle);
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Result nvioctlNvmap_FromID(u32 fd, u32 id, u32 *nvmap_handle);
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Result nvioctlNvmap_Alloc(u32 fd, u32 nvmap_handle, u32 heapmask, u32 flags, u32 align, u8 kind, void* addr);
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Result nvioctlNvmap_GetID(u32 fd, u32 nvmap_handle, u32 *id);
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Result nvioctlChannel_SetNvmapFd(u32 fd, u32 nvmap_fd);
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Result nvioctlChannel_SubmitGPFIFO(u32 fd, nvioctl_gpfifo_entry *entries, u32 num_entries, u32 flags, nvioctl_fence *fence_out);
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Result nvioctlChannel_AllocObjCtx(u32 fd, u32 class_num, u32 flags);
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Result nvioctlChannel_ZCullBind(u32 fd, u32 in[4]);
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Result nvioctlChannel_SetErrorNotifier(u32 fd, u64 offset, u64 size, u32 nvmap_handle);
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Result nvioctlChannel_SetPriority(u32 fd, u32 priority);
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Result nvioctlChannel_AllocGPFIFOEx2(u32 fd, u32 num_entries, u32 flags, u32 unk0, u32 unk1, u32 unk2, u32 unk3, nvioctl_fence *fence_out);
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Result nvioctlChannel_SetUserData(u32 fd, void* addr);
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