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2 Commits

Author SHA1 Message Date
liamadvance
0094af6d29 crypto: fix aes-cbc individual block decryption 2023-10-21 21:20:57 +02:00
p-sam
ae491ce57b Add GetPossibleClockRates method for pcv and clkrst 2023-10-21 16:55:34 +02:00
5 changed files with 61 additions and 6 deletions

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@ -27,3 +27,4 @@ Result clkrstOpenSession(ClkrstSession* session_out, PcvModuleId module_id, u32
void clkrstCloseSession(ClkrstSession* session);
Result clkrstSetClockRate(ClkrstSession* session, u32 hz);
Result clkrstGetClockRate(ClkrstSession* session, u32 *out_hz);
Result clkrstGetPossibleClockRates(ClkrstSession *session, u32 *rates, s32 max_count, PcvClockRatesListType *out_type, s32 *out_count);

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@ -191,6 +191,13 @@ typedef enum {
PcvModuleId_EXTPERIPH2 = 0x40000057,
} PcvModuleId;
// Clock list type returned by GetPossibleClockRates
typedef enum {
PcvClockRatesListType_Invalid = 0,
PcvClockRatesListType_Discrete = 1,
PcvClockRatesListType_Range = 2,
} PcvClockRatesListType;
/// Initialize pcv.
Result pcvInitialize(void);
@ -210,3 +217,5 @@ Result pcvSetClockRate(PcvModule module, u32 hz);
Result pcvSetVoltageEnabled(u32 power_domain, bool state);
/// Only available on [1.0.0-7.0.1].
Result pcvGetVoltageEnabled(bool *isEnabled, u32 power_domain);
/// Only available on [1.0.0-7.0.1].
Result pcvGetPossibleClockRates(PcvModule module, u32 *rates, s32 max_count, PcvClockRatesListType *out_type, s32 *out_count);

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@ -261,8 +261,9 @@ static inline void _aes128CbcDecryptBlocks(Aes128CbcContext *ctx, u8 *dst_u8, co
AES_ENC_DEC_INPUT_ROUND_KEY(10)
);
/* Update IV. */
cur_iv = tmp0;
/* Do XOR for CBC. */
tmp0 = veorq_u8(tmp0, cur_iv);
cur_iv = block0;
/* Store to output. */
vst1q_u8(dst_u8, tmp0);
@ -478,8 +479,9 @@ static inline void _aes192CbcDecryptBlocks(Aes192CbcContext *ctx, u8 *dst_u8, co
AES_ENC_DEC_INPUT_ROUND_KEY(12)
);
/* Update IV. */
cur_iv = tmp0;
/* Do XOR for CBC. */
tmp0 = veorq_u8(tmp0, cur_iv);
cur_iv = block0;
/* Store to output. */
vst1q_u8(dst_u8, tmp0);
@ -711,8 +713,9 @@ static inline void _aes256CbcDecryptBlocks(Aes256CbcContext *ctx, u8 *dst_u8, co
AES_ENC_DEC_INPUT_ROUND_KEY(14)
);
/* Update IV. */
cur_iv = tmp0;
/* Do XOR for CBC. */
tmp0 = veorq_u8(tmp0, cur_iv);
cur_iv = block0;
/* Store to output. */
vst1q_u8(dst_u8, tmp0);

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@ -44,3 +44,20 @@ Result clkrstSetClockRate(ClkrstSession* session, u32 hz) {
Result clkrstGetClockRate(ClkrstSession* session, u32 *out_hz) {
return serviceDispatchOut(&session->s, 8, *out_hz);
}
Result clkrstGetPossibleClockRates(ClkrstSession *session, u32 *rates, s32 max_count, PcvClockRatesListType *out_type, s32 *out_count) {
struct {
s32 type;
s32 count;
} out;
Result rc = serviceDispatchInOut(&session->s, 10, max_count, out,
.buffer_attrs = { SfBufferAttr_Out | SfBufferAttr_HipcAutoSelect, },
.buffers = { { rates, max_count * sizeof(u32) }, }
);
if (R_SUCCEEDED(rc) && out_type) *out_type = out.type;
if (R_SUCCEEDED(rc) && out_count) *out_count = out.count;
return rc;
}

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@ -94,3 +94,28 @@ Result pcvGetVoltageEnabled(bool *isEnabled, u32 power_domain) {
return rc;
}
Result pcvGetPossibleClockRates(PcvModule module, u32 *rates, s32 max_count, PcvClockRatesListType *out_type, s32 *out_count) {
if(hosversionAtLeast(8,0,0))
return MAKERESULT(Module_Libnx, LibnxError_IncompatSysVer);
const struct {
PcvModule module;
s32 max_count;
} in = { module, max_count };
struct {
s32 type;
s32 count;
} out;
Result rc = serviceDispatchInOut(&g_pcvSrv, 5, in, out,
.buffer_attrs = { SfBufferAttr_Out | SfBufferAttr_HipcPointer, },
.buffers = { { rates, max_count * sizeof(u32) }, }
);
if (R_SUCCEEDED(rc) && out_type) *out_type = out.type;
if (R_SUCCEEDED(rc) && out_count) *out_count = out.count;
return rc;
}