From ff5fcbceb2d30a8143f9c417987ddf4a2eaa6d89 Mon Sep 17 00:00:00 2001
From: plutoo <plutoo@universe>
Date: Sat, 10 Mar 2018 15:44:04 +0100
Subject: [PATCH] Implement 3d_ctx

---
 nx/include/switch/nvidia/gpu/3d_ctx.h | 1 +
 nx/include/switch/nvidia/ioctl.h      | 2 +-
 nx/source/display/nvgfx.c             | 2 +-
 nx/source/nvidia/gpu/3d_ctx.c         | 6 ++++--
 nx/source/nvidia/ioctl/nvchannel.c    | 7 ++++---
 5 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/nx/include/switch/nvidia/gpu/3d_ctx.h b/nx/include/switch/nvidia/gpu/3d_ctx.h
index 15709836..04989f93 100644
--- a/nx/include/switch/nvidia/gpu/3d_ctx.h
+++ b/nx/include/switch/nvidia/gpu/3d_ctx.h
@@ -2,6 +2,7 @@ typedef struct NvGpu NvGpu;
 
 typedef struct {
     NvGpu* parent;
+    u64    obj_id;
 } Nv3dContext;
 
 Result nv3dCreate(Nv3dContext* t, NvGpu* parent);
diff --git a/nx/include/switch/nvidia/ioctl.h b/nx/include/switch/nvidia/ioctl.h
index df3e337b..f1839032 100644
--- a/nx/include/switch/nvidia/ioctl.h
+++ b/nx/include/switch/nvidia/ioctl.h
@@ -144,7 +144,7 @@ Result nvioctlNvmap_GetId(u32 fd, u32 nvmap_handle, u32 *id);
 
 Result nvioctlChannel_SetNvmapFd(u32 fd, u32 nvmap_fd);
 Result nvioctlChannel_SubmitGpfifo(u32 fd, nvioctl_gpfifo_entry *entries, u32 num_entries, u32 flags, nvioctl_fence *fence_out);
-Result nvioctlChannel_AllocObjCtx(u32 fd, u32 class_num, u32 flags);
+Result nvioctlChannel_AllocObjCtx(u32 fd, u32 class_num, u32 flags, u64* id_out);
 Result nvioctlChannel_ZCullBind(u32 fd, u64 gpu_va, u32 mode);
 Result nvioctlChannel_SetErrorNotifier(u32 fd, u64 offset, u64 size, u32 nvmap_handle);
 Result nvioctlChannel_SetPriority(u32 fd, u32 priority);
diff --git a/nx/source/display/nvgfx.c b/nx/source/display/nvgfx.c
index ac4ebcd7..fff53296 100644
--- a/nx/source/display/nvgfx.c
+++ b/nx/source/display/nvgfx.c
@@ -131,7 +131,7 @@ Result nvgfxInitialize(void) {
 
     if (R_SUCCEEDED(rc)) rc = nvioctlChannel_AllocGpfifoEx2(g_nvgfx_fd_nvhostgpu, 0x800, 0x1, 0, 0, 0, 0, &g_nvgfx_nvhost_fence);
 
-    if (R_SUCCEEDED(rc)) rc = nvioctlChannel_AllocObjCtx(g_nvgfx_fd_nvhostgpu, g_nvgfx_gpu_characteristics.threed_class, 0);
+    if (R_SUCCEEDED(rc)) rc = nvioctlChannel_AllocObjCtx(g_nvgfx_fd_nvhostgpu, g_nvgfx_gpu_characteristics.threed_class, 0, NULL);
     if (R_SUCCEEDED(rc)) rc = nvioctlChannel_SetPriority(g_nvgfx_fd_nvhostgpu, NvChannelPriority_Medium);
 
     if (R_SUCCEEDED(rc)) rc = nvmapobjSetup(&nvmap_objs[4], 0, 0x1, 0x20000, 0);
diff --git a/nx/source/nvidia/gpu/3d_ctx.c b/nx/source/nvidia/gpu/3d_ctx.c
index 1faa4ba4..bac68fdb 100644
--- a/nx/source/nvidia/gpu/3d_ctx.c
+++ b/nx/source/nvidia/gpu/3d_ctx.c
@@ -3,9 +3,11 @@
 Result nv3dCreate(Nv3dContext* t, NvGpu* parent)
 {
     t->parent = parent;
-    return 0;
+
+    // TODO: Get class number from nvinfo*().
+    return nvioctlChannel_AllocObjCtx(parent->gpu_channel.fd, 0xB197, 0, &t->obj_id);
 }
 
 void nv3dClose(Nv3dContext* t) {
-    /**/
+    // Empty
 }
diff --git a/nx/source/nvidia/ioctl/nvchannel.c b/nx/source/nvidia/ioctl/nvchannel.c
index ebe81cc6..80665580 100644
--- a/nx/source/nvidia/ioctl/nvchannel.c
+++ b/nx/source/nvidia/ioctl/nvchannel.c
@@ -46,17 +46,18 @@ Result nvioctlChannel_SubmitGpfifo(u32 fd, nvioctl_gpfifo_entry *entries, u32 nu
     return rc;
 }
 
-Result nvioctlChannel_AllocObjCtx(u32 fd, u32 class_num, u32 flags) {
+Result nvioctlChannel_AllocObjCtx(u32 fd, u32 class_num, u32 flags, u64* id_out) {
     struct {
         __nv_in u32 class_num;
         __nv_in u32 flags;
-        __nv_in u64 obj_id;  // (ignored) used for FREE_OBJ_CTX ioctl, which is not supported
+        __nv_out u64 obj_id;  // (ignored) used for FREE_OBJ_CTX ioctl, which is not supported
     } data;
 
     memset(&data, 0, sizeof(data));
     data.class_num = class_num;
     data.flags = flags;
-    data.obj_id = 0xDEADBEEF;
+    if (id_out != NULL)
+        *id_out = data.obj_id;
 
     return nvIoctl(fd, _NV_IOWR(0x48, 0x09, data), &data);
 }