From fba43b0f103aaae62958e4e7e5f079824740b0d8 Mon Sep 17 00:00:00 2001
From: fincs <fincs.alt1@gmail.com>
Date: Wed, 17 Oct 2018 00:32:47 +0200
Subject: [PATCH] nvBufferCreate: use separate
 is_cpu_cacheable/is_gpu_cacheable parameters

---
 nx/include/switch/nvidia/buffer.h |  5 +++--
 nx/source/nvidia/buffer.c         | 15 ++++++++-------
 nx/source/nvidia/gpu/cmd_list.c   |  2 +-
 nx/source/nvidia/gpu/zcull_ctx.c  |  2 +-
 4 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/nx/include/switch/nvidia/buffer.h b/nx/include/switch/nvidia/buffer.h
index 6a85b2dc..5557dd54 100644
--- a/nx/include/switch/nvidia/buffer.h
+++ b/nx/include/switch/nvidia/buffer.h
@@ -13,14 +13,15 @@ typedef struct NvBuffer {
     NvAddressSpace* addr_space;
     NvKind kind;
     bool   has_init;
-    bool   is_cacheable;
+    bool   is_cpu_cacheable;
+    bool   is_gpu_cacheable;
 } NvBuffer;
 
 Result nvBufferInit(void);
 u32    nvBufferGetNvmapFd(void);
 void   nvBufferExit(void);
 
-Result nvBufferCreate(NvBuffer* m, size_t size, u32 align, bool is_cacheable, NvKind kind, NvAddressSpace* as);
+Result nvBufferCreate(NvBuffer* m, size_t size, u32 align, bool is_cpu_cacheable, bool is_gpu_cacheable, NvKind kind, NvAddressSpace* as);
 void   nvBufferFree(NvBuffer* m);
 
 void*  nvBufferGetCpuAddr(NvBuffer* m);
diff --git a/nx/source/nvidia/buffer.c b/nx/source/nvidia/buffer.c
index af38dfb7..dfd149e6 100644
--- a/nx/source/nvidia/buffer.c
+++ b/nx/source/nvidia/buffer.c
@@ -43,7 +43,7 @@ u32 nvBufferGetNvmapFd(void) {
 }
 
 Result nvBufferCreate(
-    NvBuffer* m, size_t size, u32 align, bool is_cacheable, NvKind kind,
+    NvBuffer* m, size_t size, u32 align, bool is_cpu_cacheable, bool is_gpu_cacheable, NvKind kind,
     NvAddressSpace* as)
 {
     Result rc;
@@ -51,7 +51,8 @@ Result nvBufferCreate(
     size = (size + align - 1) & ~(align - 1);
 
     m->has_init = true;
-    m->is_cacheable = is_cacheable;
+    m->is_cpu_cacheable = is_cpu_cacheable;
+    m->is_gpu_cacheable = is_gpu_cacheable;
     m->size = size;
     m->fd = -1;
     m->cpu_addr = memalign(align, size);
@@ -67,16 +68,16 @@ Result nvBufferCreate(
 
     if (R_SUCCEEDED(rc))
         rc = nvioctlNvmap_Alloc(g_nvmap_fd, m->fd,
-            0, is_cacheable ? 1 : 0, align, kind, m->cpu_addr);
+            0, is_cpu_cacheable ? 1 : 0, align, kind, m->cpu_addr);
 
-    if (R_SUCCEEDED(rc) && !is_cacheable) {
+    if (R_SUCCEEDED(rc) && !is_cpu_cacheable) {
         armDCacheFlush(m->cpu_addr, m->size);
         svcSetMemoryAttribute(m->cpu_addr, m->size, 8, 8);
     }
 
     if (R_SUCCEEDED(rc))
         rc = nvAddressSpaceMapBuffer(as, m->fd,
-            is_cacheable ? NvMapBufferFlags_IsCacheable : 0, NvKind_Pitch, &m->gpu_addr);
+            is_gpu_cacheable ? NvMapBufferFlags_IsCacheable : 0, NvKind_Pitch, &m->gpu_addr);
 
     if (R_FAILED(rc))
         nvBufferFree(m);
@@ -105,7 +106,7 @@ void nvBufferFree(NvBuffer* m)
     }
 
     if (m->cpu_addr) {
-        if (!m->is_cacheable)
+        if (!m->is_cpu_cacheable)
             svcSetMemoryAttribute(m->cpu_addr, m->size, 8, 0);
 
         free(m->cpu_addr);
@@ -125,7 +126,7 @@ iova_t nvBufferGetGpuAddr(NvBuffer* m) {
 
 Result nvBufferMapAsTexture(NvBuffer* m, NvKind kind) {
     return nvAddressSpaceMapBuffer(m->addr_space, m->fd,
-        m->is_cacheable ? NvMapBufferFlags_IsCacheable : 0, kind, &m->gpu_addr_texture);
+        m->is_gpu_cacheable ? NvMapBufferFlags_IsCacheable : 0, kind, &m->gpu_addr_texture);
 }
 
 iova_t nvBufferGetGpuAddrTexture(NvBuffer* m) {
diff --git a/nx/source/nvidia/gpu/cmd_list.c b/nx/source/nvidia/gpu/cmd_list.c
index ff6fc50a..06cf3099 100644
--- a/nx/source/nvidia/gpu/cmd_list.c
+++ b/nx/source/nvidia/gpu/cmd_list.c
@@ -22,7 +22,7 @@ Result nvCmdListCreate(NvCmdList* c, NvGpu* parent, size_t max_cmds)
     Result rc;
 
     rc = nvBufferCreate(
-        &c->buffer, max_cmds * 4, 0x1000, NvKind_Pitch, false,
+        &c->buffer, max_cmds * 4, 0x1000, NvKind_Pitch, false, false,
         &parent->addr_space);
 
     if (R_SUCCEEDED(rc)) {
diff --git a/nx/source/nvidia/gpu/zcull_ctx.c b/nx/source/nvidia/gpu/zcull_ctx.c
index 7c3110df..ae080bd8 100644
--- a/nx/source/nvidia/gpu/zcull_ctx.c
+++ b/nx/source/nvidia/gpu/zcull_ctx.c
@@ -25,7 +25,7 @@ Result nvZcullContextCreate(NvZcullContext* z, NvGpu* parent)
     z->parent = parent;
 
     rc = nvBufferCreate(
-        &z->ctx_buf, nvInfoGetZcullCtxSize(), 0x20000, NvKind_Pitch, true,
+        &z->ctx_buf, nvInfoGetZcullCtxSize(), 0x20000, NvKind_Pitch, false, true,
         &parent->addr_space);
 
     if (R_SUCCEEDED(rc))