From f60f82856ac84170fea6c5ff350402b1ebc1a00a Mon Sep 17 00:00:00 2001 From: Michael Scire Date: Tue, 22 Mar 2022 09:36:25 -0700 Subject: [PATCH] cache: set flag in tlr when doing maintenance --- nx/source/arm/cache.s | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/nx/source/arm/cache.s b/nx/source/arm/cache.s index f3495c00..c5ed394b 100644 --- a/nx/source/arm/cache.s +++ b/nx/source/arm/cache.s @@ -22,6 +22,10 @@ CODE_BEGIN armDCacheFlush bic x8, x0, x10 mov x10, x1 + mov w1, #1 + mrs x0, tpidrro_el0 + strb w1, [x0, #0x104] + armDCacheFlush_L0: dc civac, x8 add x8, x8, x9 @@ -29,6 +33,9 @@ armDCacheFlush_L0: bcc armDCacheFlush_L0 dsb sy + + strb wzr, [x0, #0x104] + ret CODE_END @@ -43,6 +50,10 @@ CODE_BEGIN armDCacheClean bic x8, x0, x10 mov x10, x1 + mov w1, #1 + mrs x0, tpidrro_el0 + strb w1, [x0, #0x104] + armDCacheClean_L0: dc cvac, x8 add x8, x8, x9 @@ -50,6 +61,9 @@ armDCacheClean_L0: bcc armDCacheClean_L0 dsb sy + + strb wzr, [x0, #0x104] + ret CODE_END @@ -63,6 +77,10 @@ CODE_BEGIN armICacheInvalidate bic x8, x0, x10 mov x10, x1 + mov w1, #1 + mrs x0, tpidrro_el0 + strb w1, [x0, #0x104] + armICacheInvalidate_L0: ic ivau, x8 add x8, x8, x9 @@ -70,6 +88,9 @@ armICacheInvalidate_L0: bcc armICacheInvalidate_L0 dsb sy + + strb wzr, [x0, #0x104] + ret CODE_END @@ -84,6 +105,10 @@ CODE_BEGIN armDCacheZero bic x8, x0, x10 mov x10, x1 + mov w1, #1 + mrs x0, tpidrro_el0 + strb w1, [x0, #0x104] + armDCacheZero_L0: dc zva, x8 add x8, x8, x9 @@ -91,5 +116,8 @@ armDCacheZero_L0: bcc armDCacheZero_L0 dsb sy + + strb wzr, [x0, #0x104] + ret CODE_END