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Handle nvioctlChannel_ZCullBind() properly.
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@ -101,7 +101,7 @@ Result nvioctlNvmap_GetId(u32 fd, u32 nvmap_handle, u32 *id);
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Result nvioctlChannel_SetNvmapFd(u32 fd, u32 nvmap_fd);
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Result nvioctlChannel_SetNvmapFd(u32 fd, u32 nvmap_fd);
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Result nvioctlChannel_SubmitGpfifo(u32 fd, nvioctl_gpfifo_entry *entries, u32 num_entries, u32 flags, nvioctl_fence *fence_out);
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Result nvioctlChannel_SubmitGpfifo(u32 fd, nvioctl_gpfifo_entry *entries, u32 num_entries, u32 flags, nvioctl_fence *fence_out);
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Result nvioctlChannel_AllocObjCtx(u32 fd, u32 class_num, u32 flags);
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Result nvioctlChannel_AllocObjCtx(u32 fd, u32 class_num, u32 flags);
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Result nvioctlChannel_ZCullBind(u32 fd, u32 in[4]);
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Result nvioctlChannel_ZCullBind(u32 fd, u64 gpu_va, u32 mode);
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Result nvioctlChannel_SetErrorNotifier(u32 fd, u64 offset, u64 size, u32 nvmap_handle);
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Result nvioctlChannel_SetErrorNotifier(u32 fd, u64 offset, u64 size, u32 nvmap_handle);
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Result nvioctlChannel_SetPriority(u32 fd, u32 priority);
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Result nvioctlChannel_SetPriority(u32 fd, u32 priority);
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Result nvioctlChannel_AllocGpfifoEx2(u32 fd, u32 num_entries, u32 flags, u32 unk0, u32 unk1, u32 unk2, u32 unk3, nvioctl_fence *fence_out);
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Result nvioctlChannel_AllocGpfifoEx2(u32 fd, u32 num_entries, u32 flags, u32 unk0, u32 unk1, u32 unk2, u32 unk3, nvioctl_fence *fence_out);
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@ -58,14 +58,16 @@ Result nvioctlChannel_AllocObjCtx(u32 fd, u32 class_num, u32 flags) {
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return nvIoctl(fd, _IOWR(0x48, 0x09, data), &data);
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return nvIoctl(fd, _IOWR(0x48, 0x09, data), &data);
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}
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}
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Result nvioctlChannel_ZCullBind(u32 fd, u32 in[4]) {
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Result nvioctlChannel_ZCullBind(u32 fd, u64 gpu_va, u32 mode) {
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// Fixme: Needs work
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struct {
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struct {
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u32 in[4];
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__in u64 gpu_va;
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__in u32 mode;
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__in u32 padding;
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} data;
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} data;
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memset(&data, 0, sizeof(data));
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memset(&data, 0, sizeof(data));
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memcpy(data.in, in, sizeof(data.in));
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data.gpu_va = gpu_va;
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data.mode = mode;
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return nvIoctl(fd, _IOWR(0x48, 0x0B, data), &data);
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return nvIoctl(fd, _IOWR(0x48, 0x0B, data), &data);
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}
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}
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@ -38,6 +38,7 @@ size_t g_nvgfx_singleframebuf_size = /*0x3c0000*/ 1280*768*4;
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static nvmapobj nvmap_objs[18];
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static nvmapobj nvmap_objs[18];
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static u64 nvmap_obj4_mapbuffer_x0_offset;
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static u64 nvmap_obj6_mapbuffer_xdb_offset;
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static u64 nvmap_obj6_mapbuffer_xdb_offset;
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//Some of this struct is based on tegra_dc_ext_flip_windowattr.
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//Some of this struct is based on tegra_dc_ext_flip_windowattr.
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@ -129,7 +130,6 @@ Result nvgfxInitialize(void) {
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u64 *ptr64 = (u64*)g_gfxprod_BufferInitData;
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u64 *ptr64 = (u64*)g_gfxprod_BufferInitData;
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if(g_nvgfxInitialized)return 0;
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if(g_nvgfxInitialized)return 0;
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u32 zcullbind_data[4] = {0x58000, 0x5, 0x2, 0x0};
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u32 framebuf_nvmap_handle = 0;//Special handle ID for framebuf/windowbuf.
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u32 framebuf_nvmap_handle = 0;//Special handle ID for framebuf/windowbuf.
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//nvioctl_gpfifo_entry gpfifo_entries[2] = {{0x00030000, 0x00177a05}, {0x00031778, 0x80002e05}};
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//nvioctl_gpfifo_entry gpfifo_entries[2] = {{0x00030000, 0x00177a05}, {0x00031778, 0x80002e05}};
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@ -155,6 +155,7 @@ Result nvgfxInitialize(void) {
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memset(&g_nvgfx_nvhostgpu_gpfifo_fence, 0, sizeof(g_nvgfx_nvhostgpu_gpfifo_fence));
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memset(&g_nvgfx_nvhostgpu_gpfifo_fence, 0, sizeof(g_nvgfx_nvhostgpu_gpfifo_fence));
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g_nvgfx_nvhostasgpu_allocspace_offset = 0;
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g_nvgfx_nvhostasgpu_allocspace_offset = 0;
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g_nvgfx_zcullctxsize = 0;
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g_nvgfx_zcullctxsize = 0;
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nvmap_obj4_mapbuffer_x0_offset = 0;
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nvmap_obj6_mapbuffer_xdb_offset = 0;
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nvmap_obj6_mapbuffer_xdb_offset = 0;
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g_nvgfx_nvhostctrl_eventres = 0;
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g_nvgfx_nvhostctrl_eventres = 0;
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@ -246,10 +247,10 @@ Result nvgfxInitialize(void) {
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if (R_SUCCEEDED(rc)) rc = nvmapobjSetup(&nvmap_objs[4], 0, 0x1, 0x20000, 0);
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if (R_SUCCEEDED(rc)) rc = nvmapobjSetup(&nvmap_objs[4], 0, 0x1, 0x20000, 0);
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if (R_SUCCEEDED(rc)) rc = nvioctlNvhostAsGpu_MapBufferEx(g_nvgfx_fd_nvhostasgpu, 4, 0, nvmap_objs[4].handle, 0x10000, 0, 0, 0, NULL);
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if (R_SUCCEEDED(rc)) rc = nvioctlNvhostAsGpu_MapBufferEx(g_nvgfx_fd_nvhostasgpu, 4, 0, nvmap_objs[4].handle, 0x10000, 0, 0, 0, &nvmap_obj4_mapbuffer_x0_offset);
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if (R_SUCCEEDED(rc)) rc = nvioctlNvhostAsGpu_MapBufferEx(g_nvgfx_fd_nvhostasgpu, 4, 0xfe, nvmap_objs[4].handle, 0x10000, 0, 0, 0, NULL);
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if (R_SUCCEEDED(rc)) rc = nvioctlNvhostAsGpu_MapBufferEx(g_nvgfx_fd_nvhostasgpu, 4, 0xfe, nvmap_objs[4].handle, 0x10000, 0, 0, 0, NULL);
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if (R_SUCCEEDED(rc)) rc = nvioctlChannel_ZCullBind(g_nvgfx_fd_nvhostgpu, zcullbind_data);
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if (R_SUCCEEDED(rc)) rc = nvioctlChannel_ZCullBind(g_nvgfx_fd_nvhostgpu, nvmap_obj4_mapbuffer_x0_offset+0x8000, 0x2);
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//Officially, ipcQueryPointerBufferSize and NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO(nvioctlChannel_SubmitGPFIFO) are used here with the duplicate service session setup during nv serv init.
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//Officially, ipcQueryPointerBufferSize and NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO(nvioctlChannel_SubmitGPFIFO) are used here with the duplicate service session setup during nv serv init.
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//TODO: This is probably used for GPU rendering? Is this really needed when not doing actual GPU rendering?
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//TODO: This is probably used for GPU rendering? Is this really needed when not doing actual GPU rendering?
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