diff --git a/nx/include/switch/display/buffer_producer.h b/nx/include/switch/display/buffer_producer.h index 71200c79..425b696b 100644 --- a/nx/include/switch/display/buffer_producer.h +++ b/nx/include/switch/display/buffer_producer.h @@ -1,5 +1,5 @@ #pragma once -#include "../display/nvioctl.h" +#include "../nvidia/ioctl.h" typedef struct { u32 is_valid; diff --git a/nx/include/switch/display/ioctl.h b/nx/include/switch/display/ioctl.h deleted file mode 100644 index 5af60893..00000000 --- a/nx/include/switch/display/ioctl.h +++ /dev/null @@ -1,47 +0,0 @@ -#pragma once - -//The below defines are based on Linux kernel ioctl.h. - -#define _NV_IOC_NRBITS 8 -#define _NV_IOC_TYPEBITS 8 -#define _NV_IOC_SIZEBITS 14 -#define _NV_IOC_DIRBITS 2 - -#define _NV_IOC_NRMASK ((1 << _NV_IOC_NRBITS)-1) -#define _NV_IOC_TYPEMASK ((1 << _NV_IOC_TYPEBITS)-1) -#define _NV_IOC_SIZEMASK ((1 << _NV_IOC_SIZEBITS)-1) -#define _NV_IOC_DIRMASK ((1 << _NV_IOC_DIRBITS)-1) - -#define _NV_IOC_NRSHIFT 0 -#define _NV_IOC_TYPESHIFT (_NV_IOC_NRSHIFT+_NV_IOC_NRBITS) -#define _NV_IOC_SIZESHIFT (_NV_IOC_TYPESHIFT+_NV_IOC_TYPEBITS) -#define _NV_IOC_DIRSHIFT (_NV_IOC_SIZESHIFT+_NV_IOC_SIZEBITS) - -/* - * Direction bits. - */ -#define _NV_IOC_NONE 0U -#define _NV_IOC_WRITE 1U -#define _NV_IOC_READ 2U - -#define _NV_IOC(dir,type,nr,size) \ - (((dir) << _NV_IOC_DIRSHIFT) | \ - ((type) << _NV_IOC_TYPESHIFT) | \ - ((nr) << _NV_IOC_NRSHIFT) | \ - ((size) << _NV_IOC_SIZESHIFT)) - -/* used to create numbers */ -#define _NV_IO(type,nr) _NV_IOC(_NV_IOC_NONE,(type),(nr),0) -#define _NV_IOR(type,nr,size) _NV_IOC(_NV_IOC_READ,(type),(nr),sizeof(size)) -#define _NV_IOW(type,nr,size) _NV_IOC(_NV_IOC_WRITE,(type),(nr),sizeof(size)) -#define _NV_IOWR(type,nr,size) _NV_IOC(_NV_IOC_READ|_NV_IOC_WRITE,(type),(nr),sizeof(size)) - -/* used to decode ioctl numbers.. */ -#define _NV_IOC_DIR(nr) (((nr) >> _NV_IOC_DIRSHIFT) & _NV_IOC_DIRMASK) -#define _NV_IOC_TYPE(nr) (((nr) >> _NV_IOC_TYPESHIFT) & _NV_IOC_TYPEMASK) -#define _NV_IOC_NR(nr) (((nr) >> _NV_IOC_NRSHIFT) & _NV_IOC_NRMASK) -#define _NV_IOC_SIZE(nr) (((nr) >> _NV_IOC_SIZESHIFT) & _NV_IOC_SIZEMASK) - -#define __nv_in -#define __nv_out -#define __nv_inout diff --git a/nx/include/switch/display/nvioctl.h b/nx/include/switch/nvidia/ioctl.h similarity index 74% rename from nx/include/switch/display/nvioctl.h rename to nx/include/switch/nvidia/ioctl.h index 24c75e0c..df3e337b 100644 --- a/nx/include/switch/display/nvioctl.h +++ b/nx/include/switch/nvidia/ioctl.h @@ -1,6 +1,49 @@ #pragma once #include "../types.h" +// The below defines are based on Linux kernel ioctl.h. +#define _NV_IOC_NRBITS 8 +#define _NV_IOC_TYPEBITS 8 +#define _NV_IOC_SIZEBITS 14 +#define _NV_IOC_DIRBITS 2 + +#define _NV_IOC_NRMASK ((1 << _NV_IOC_NRBITS)-1) +#define _NV_IOC_TYPEMASK ((1 << _NV_IOC_TYPEBITS)-1) +#define _NV_IOC_SIZEMASK ((1 << _NV_IOC_SIZEBITS)-1) +#define _NV_IOC_DIRMASK ((1 << _NV_IOC_DIRBITS)-1) + +#define _NV_IOC_NRSHIFT 0 +#define _NV_IOC_TYPESHIFT (_NV_IOC_NRSHIFT+_NV_IOC_NRBITS) +#define _NV_IOC_SIZESHIFT (_NV_IOC_TYPESHIFT+_NV_IOC_TYPEBITS) +#define _NV_IOC_DIRSHIFT (_NV_IOC_SIZESHIFT+_NV_IOC_SIZEBITS) + +// Direction bits. +#define _NV_IOC_NONE 0U +#define _NV_IOC_WRITE 1U +#define _NV_IOC_READ 2U + +#define _NV_IOC(dir,type,nr,size) \ + (((dir) << _NV_IOC_DIRSHIFT) | \ + ((type) << _NV_IOC_TYPESHIFT) | \ + ((nr) << _NV_IOC_NRSHIFT) | \ + ((size) << _NV_IOC_SIZESHIFT)) + +/* used to create numbers */ +#define _NV_IO(type,nr) _NV_IOC(_NV_IOC_NONE,(type),(nr),0) +#define _NV_IOR(type,nr,size) _NV_IOC(_NV_IOC_READ,(type),(nr),sizeof(size)) +#define _NV_IOW(type,nr,size) _NV_IOC(_NV_IOC_WRITE,(type),(nr),sizeof(size)) +#define _NV_IOWR(type,nr,size) _NV_IOC(_NV_IOC_READ|_NV_IOC_WRITE,(type),(nr),sizeof(size)) + +/* used to decode ioctl numbers.. */ +#define _NV_IOC_DIR(nr) (((nr) >> _NV_IOC_DIRSHIFT) & _NV_IOC_DIRMASK) +#define _NV_IOC_TYPE(nr) (((nr) >> _NV_IOC_TYPESHIFT) & _NV_IOC_TYPEMASK) +#define _NV_IOC_NR(nr) (((nr) >> _NV_IOC_NRSHIFT) & _NV_IOC_NRMASK) +#define _NV_IOC_SIZE(nr) (((nr) >> _NV_IOC_SIZESHIFT) & _NV_IOC_SIZEMASK) + +#define __nv_in +#define __nv_out +#define __nv_inout + typedef struct { u32 arch; // 0x120 (NVGPU_GPU_ARCH_GM200) u32 impl; // 0xB (NVGPU_GPU_IMPL_GM20B) @@ -37,7 +80,7 @@ typedef struct { u32 rop_l2_en_mask_1; // 0x0 u64 chipname; // 0x6230326D67 ("gm20b") u64 gr_compbit_store_base_hw; // 0x0 (not supported) -} gpu_characteristics; +} nvioctl_gpu_characteristics; typedef struct { u64 offset; @@ -84,7 +127,7 @@ Result nvioctlNvhostCtrl_EventRegister(u32 fd, u32 event_id); Result nvioctlNvhostCtrlGpu_ZCullGetCtxSize(u32 fd, u32 *out); Result nvioctlNvhostCtrlGpu_ZCullGetInfo(u32 fd, u32 out[40>>2]); -Result nvioctlNvhostCtrlGpu_GetCharacteristics(u32 fd, gpu_characteristics *out); +Result nvioctlNvhostCtrlGpu_GetCharacteristics(u32 fd, nvioctl_gpu_characteristics *out); Result nvioctlNvhostCtrlGpu_GetTpcMasks(u32 fd, u32 inval, u32 out[24>>2]); Result nvioctlNvhostCtrlGpu_GetL2State(u32 fd, nvioctl_l2_state *out); diff --git a/nx/include/switch/nvidia/nvmap.h b/nx/include/switch/nvidia/nvmap.h new file mode 100644 index 00000000..f06583d5 --- /dev/null +++ b/nx/include/switch/nvidia/nvmap.h @@ -0,0 +1,256 @@ +#include "../types.h" + +typedef struct { + u32 fd; + u32 size; + void* ptr; +} Nvmap; + +typedef enum { + NvmapFlags_Writable=1 +} NvmapFlags; + +typedef enum { + NvmapKind_PitCh=0x0, + NvmapKind_Z16=0x1, + NvmapKind_Z16_2C=0x2, + NvmapKind_Z16_MS2_2C=0x3, + NvmapKind_Z16_MS4_2C=0x4, + NvmapKind_Z16_MS8_2C=0x5, + NvmapKind_Z16_MS16_2C=0x6, + NvmapKind_Z16_2Z=0x7, + NvmapKind_Z16_MS2_2Z=0x8, + NvmapKind_Z16_MS4_2Z=0x9, + NvmapKind_Z16_MS8_2Z=0xa, + NvmapKind_Z16_MS16_2Z=0xb, + NvmapKind_Z16_4CZ=0xC, + NvmapKind_Z16_MS2_4CZ=0xd, + NvmapKind_Z16_MS4_4CZ=0xe, + NvmapKind_Z16_MS8_4CZ=0xf, + NvmapKind_Z16_MS16_4CZ=0x10, + NvmapKind_S8Z24=0x11, + NvmapKind_S8Z24_1Z=0x12, + NvmapKind_S8Z24_MS2_1Z=0x13, + NvmapKind_S8Z24_MS4_1Z=0x14, + NvmapKind_S8Z24_MS8_1Z=0x15, + NvmapKind_S8Z24_MS16_1Z=0x16, + NvmapKind_S8Z24_2CZ=0x17, + NvmapKind_S8Z24_MS2_2CZ=0x18, + NvmapKind_S8Z24_MS4_2CZ=0x19, + NvmapKind_S8Z24_MS8_2CZ=0x1a, + NvmapKind_S8Z24_MS16_2CZ=0x1b, + NvmapKind_S8Z24_2CS=0x1C, + NvmapKind_S8Z24_MS2_2CS=0x1d, + NvmapKind_S8Z24_MS4_2CS=0x1e, + NvmapKind_S8Z24_MS8_2CS=0x1f, + NvmapKind_S8Z24_MS16_2CS=0x20, + NvmapKind_S8Z24_4CSZV=0x21, + NvmapKind_S8Z24_MS2_4CSZV=0x22, + NvmapKind_S8Z24_MS4_4CSZV=0x23, + NvmapKind_S8Z24_MS8_4CSZV=0x24, + NvmapKind_S8Z24_MS16_4CSZV=0x25, + NvmapKind_V8Z24_MS4_VC12=0x26, + NvmapKind_V8Z24_MS4_VC4=0x27, + NvmapKind_V8Z24_MS8_VC8=0x28, + NvmapKind_V8Z24_MS8_VC24=0x29, + NvmapKind_S8=0x2a, + NvmapKind_S8_2S=0x2b, + NvmapKind_V8Z24_MS4_VC12_1ZV=0x2e, + NvmapKind_V8Z24_MS4_VC4_1ZV=0x2f, + NvmapKind_V8Z24_MS8_VC8_1ZV=0x30, + NvmapKind_V8Z24_MS8_VC24_1ZV=0x31, + NvmapKind_V8Z24_MS4_VC12_2CS=0x32, + NvmapKind_V8Z24_MS4_VC4_2CS=0x33, + NvmapKind_V8Z24_MS8_VC8_2CS=0x34, + NvmapKind_V8Z24_MS8_VC24_2CS=0x35, + NvmapKind_V8Z24_MS4_VC12_2CZV=0x3a, + NvmapKind_V8Z24_MS4_VC4_2CZV=0x3b, + NvmapKind_V8Z24_MS8_VC8_2CZV=0x3C, + NvmapKind_V8Z24_MS8_VC24_2CZV=0x3d, + NvmapKind_V8Z24_MS4_VC12_2ZV=0x3e, + NvmapKind_V8Z24_MS4_VC4_2ZV=0x3f, + NvmapKind_V8Z24_MS8_VC8_2ZV=0x40, + NvmapKind_V8Z24_MS8_VC24_2ZV=0x41, + NvmapKind_V8Z24_MS4_VC12_4CSZV=0x42, + NvmapKind_V8Z24_MS4_VC4_4CSZV=0x43, + NvmapKind_V8Z24_MS8_VC8_4CSZV=0x44, + NvmapKind_V8Z24_MS8_VC24_4CSZV=0x45, + NvmapKind_Z24S8=0x46, + NvmapKind_Z24S8_1Z=0x47, + NvmapKind_Z24S8_MS2_1Z=0x48, + NvmapKind_Z24S8_MS4_1Z=0x49, + NvmapKind_Z24S8_MS8_1Z=0x4a, + NvmapKind_Z24S8_MS16_1Z=0x4b, + NvmapKind_Z24S8_2CS=0x4C, + NvmapKind_Z24S8_MS2_2CS=0x4d, + NvmapKind_Z24S8_MS4_2CS=0x4e, + NvmapKind_Z24S8_MS8_2CS=0x4f, + NvmapKind_Z24S8_MS16_2CS=0x50, + NvmapKind_Z24S8_2CZ=0x51, + NvmapKind_Z24S8_MS2_2CZ=0x52, + NvmapKind_Z24S8_MS4_2CZ=0x53, + NvmapKind_Z24S8_MS8_2CZ=0x54, + NvmapKind_Z24S8_MS16_2CZ=0x55, + NvmapKind_Z24S8_4CSZV=0x56, + NvmapKind_Z24S8_MS2_4CSZV=0x57, + NvmapKind_Z24S8_MS4_4CSZV=0x58, + NvmapKind_Z24S8_MS8_4CSZV=0x59, + NvmapKind_Z24S8_MS16_4CSZV=0x5a, + NvmapKind_Z24V8_MS4_VC12=0x5b, + NvmapKind_Z24V8_MS4_VC4=0x5C, + NvmapKind_Z24V8_MS8_VC8=0x5d, + NvmapKind_Z24V8_MS8_VC24=0x5e, + NvmapKind_Z24V8_MS4_VC12_1ZV=0x63, + NvmapKind_Z24V8_MS4_VC4_1ZV=0x64, + NvmapKind_Z24V8_MS8_VC8_1ZV=0x65, + NvmapKind_Z24V8_MS8_VC24_1ZV=0x66, + NvmapKind_Z24V8_MS4_VC12_2CS=0x67, + NvmapKind_Z24V8_MS4_VC4_2CS=0x68, + NvmapKind_Z24V8_MS8_VC8_2CS=0x69, + NvmapKind_Z24V8_MS8_VC24_2CS=0x6a, + NvmapKind_Z24V8_MS4_VC12_2CZV=0x6f, + NvmapKind_Z24V8_MS4_VC4_2CZV=0x70, + NvmapKind_Z24V8_MS8_VC8_2CZV=0x71, + NvmapKind_Z24V8_MS8_VC24_2CZV=0x72, + NvmapKind_Z24V8_MS4_VC12_2ZV=0x73, + NvmapKind_Z24V8_MS4_VC4_2ZV=0x74, + NvmapKind_Z24V8_MS8_VC8_2ZV=0x75, + NvmapKind_Z24V8_MS8_VC24_2ZV=0x76, + NvmapKind_Z24V8_MS4_VC12_4CSZV=0x77, + NvmapKind_Z24V8_MS4_VC4_4CSZV=0x78, + NvmapKind_Z24V8_MS8_VC8_4CSZV=0x79, + NvmapKind_Z24V8_MS8_VC24_4CSZV=0x7a, + NvmapKind_ZF32=0x7b, + NvmapKind_ZF32_1Z=0x7C, + NvmapKind_ZF32_MS2_1Z=0x7d, + NvmapKind_ZF32_MS4_1Z=0x7e, + NvmapKind_ZF32_MS8_1Z=0x7f, + NvmapKind_ZF32_MS16_1Z=0x80, + NvmapKind_ZF32_2CS=0x81, + NvmapKind_ZF32_MS2_2CS=0x82, + NvmapKind_ZF32_MS4_2CS=0x83, + NvmapKind_ZF32_MS8_2CS=0x84, + NvmapKind_ZF32_MS16_2CS=0x85, + NvmapKind_ZF32_2CZ=0x86, + NvmapKind_ZF32_MS2_2CZ=0x87, + NvmapKind_ZF32_MS4_2CZ=0x88, + NvmapKind_ZF32_MS8_2CZ=0x89, + NvmapKind_ZF32_MS16_2CZ=0x8a, + NvmapKind_X8Z24_X16V8S8_MS4_VC12=0x8b, + NvmapKind_X8Z24_X16V8S8_MS4_VC4=0x8C, + NvmapKind_X8Z24_X16V8S8_MS8_VC8=0x8d, + NvmapKind_X8Z24_X16V8S8_MS8_VC24=0x8e, + NvmapKind_X8Z24_X16V8S8_MS4_VC12_1CS=0x8f, + NvmapKind_X8Z24_X16V8S8_MS4_VC4_1CS=0x90, + NvmapKind_X8Z24_X16V8S8_MS8_VC8_1CS=0x91, + NvmapKind_X8Z24_X16V8S8_MS8_VC24_1CS=0x92, + NvmapKind_X8Z24_X16V8S8_MS4_VC12_1ZV=0x97, + NvmapKind_X8Z24_X16V8S8_MS4_VC4_1ZV=0x98, + NvmapKind_X8Z24_X16V8S8_MS8_VC8_1ZV=0x99, + NvmapKind_X8Z24_X16V8S8_MS8_VC24_1ZV=0x9a, + NvmapKind_X8Z24_X16V8S8_MS4_VC12_1CZV=0x9b, + NvmapKind_X8Z24_X16V8S8_MS4_VC4_1CZV=0x9C, + NvmapKind_X8Z24_X16V8S8_MS8_VC8_1CZV=0x9d, + NvmapKind_X8Z24_X16V8S8_MS8_VC24_1CZV=0x9e, + NvmapKind_X8Z24_X16V8S8_MS4_VC12_2CS=0x9f, + NvmapKind_X8Z24_X16V8S8_MS4_VC4_2CS=0xa0, + NvmapKind_X8Z24_X16V8S8_MS8_VC8_2CS=0xa1, + NvmapKind_X8Z24_X16V8S8_MS8_VC24_2CS=0xa2, + NvmapKind_X8Z24_X16V8S8_MS4_VC12_2CSZV=0xa3, + NvmapKind_X8Z24_X16V8S8_MS4_VC4_2CSZV=0xa4, + NvmapKind_X8Z24_X16V8S8_MS8_VC8_2CSZV=0xa5, + NvmapKind_X8Z24_X16V8S8_MS8_VC24_2CSZV=0xa6, + NvmapKind_ZF32_X16V8S8_MS4_VC12=0xa7, + NvmapKind_ZF32_X16V8S8_MS4_VC4=0xa8, + NvmapKind_ZF32_X16V8S8_MS8_VC8=0xa9, + NvmapKind_ZF32_X16V8S8_MS8_VC24=0xaa, + NvmapKind_ZF32_X16V8S8_MS4_VC12_1CS=0xab, + NvmapKind_ZF32_X16V8S8_MS4_VC4_1CS=0xaC, + NvmapKind_ZF32_X16V8S8_MS8_VC8_1CS=0xad, + NvmapKind_ZF32_X16V8S8_MS8_VC24_1CS=0xae, + NvmapKind_ZF32_X16V8S8_MS4_VC12_1ZV=0xb3, + NvmapKind_ZF32_X16V8S8_MS4_VC4_1ZV=0xb4, + NvmapKind_ZF32_X16V8S8_MS8_VC8_1ZV=0xb5, + NvmapKind_ZF32_X16V8S8_MS8_VC24_1ZV=0xb6, + NvmapKind_ZF32_X16V8S8_MS4_VC12_1CZV=0xb7, + NvmapKind_ZF32_X16V8S8_MS4_VC4_1CZV=0xb8, + NvmapKind_ZF32_X16V8S8_MS8_VC8_1CZV=0xb9, + NvmapKind_ZF32_X16V8S8_MS8_VC24_1CZV=0xba, + NvmapKind_ZF32_X16V8S8_MS4_VC12_2CS=0xbb, + NvmapKind_ZF32_X16V8S8_MS4_VC4_2CS=0xbC, + NvmapKind_ZF32_X16V8S8_MS8_VC8_2CS=0xbd, + NvmapKind_ZF32_X16V8S8_MS8_VC24_2CS=0xbe, + NvmapKind_ZF32_X16V8S8_MS4_VC12_2CSZV=0xbf, + NvmapKind_ZF32_X16V8S8_MS4_VC4_2CSZV=0xC0, + NvmapKind_ZF32_X16V8S8_MS8_VC8_2CSZV=0xC1, + NvmapKind_ZF32_X16V8S8_MS8_VC24_2CSZV=0xC2, + NvmapKind_ZF32_X24S8=0xC3, + NvmapKind_ZF32_X24S8_1CS=0xC4, + NvmapKind_ZF32_X24S8_MS2_1CS=0xC5, + NvmapKind_ZF32_X24S8_MS4_1CS=0xC6, + NvmapKind_ZF32_X24S8_MS8_1CS=0xC7, + NvmapKind_ZF32_X24S8_MS16_1CS=0xC8, + NvmapKind_SmskedMessage=0xCa, + NvmapKind_SmhostMessage=0xCb, + NvmapKind_C64_MS2_2CRA=0xCd, + NvmapKind_ZF32_X24S8_2CSZV=0xCe, + NvmapKind_ZF32_X24S8_MS2_2CSZV=0xCf, + NvmapKind_ZF32_X24S8_MS4_2CSZV=0xd0, + NvmapKind_ZF32_X24S8_MS8_2CSZV=0xd1, + NvmapKind_ZF32_X24S8_MS16_2CSZV=0xd2, + NvmapKind_ZF32_X24S8_2CS=0xd3, + NvmapKind_ZF32_X24S8_MS2_2CS=0xd4, + NvmapKind_ZF32_X24S8_MS4_2CS=0xd5, + NvmapKind_ZF32_X24S8_MS8_2CS=0xd6, + NvmapKind_ZF32_X24S8_MS16_2CS=0xd7, + NvmapKind_C32_2C=0xd8, + NvmapKind_C32_2CBR=0xd9, + NvmapKind_C32_2CBA=0xda, + NvmapKind_C32_2CRA=0xdb, + NvmapKind_C32_2BRA=0xdC, + NvmapKind_C32_MS2_2C=0xdd, + NvmapKind_C32_MS2_2CBR=0xde, + NvmapKind_C32_MS2_2CRA=0xCC, + NvmapKind_C32_MS4_2C=0xdf, + NvmapKind_C32_MS4_2CBR=0xe0, + NvmapKind_C32_MS4_2CBA=0xe1, + NvmapKind_C32_MS4_2CRA=0xe2, + NvmapKind_C32_MS4_2BRA=0xe3, + NvmapKind_C32_MS8_MS16_2C=0xe4, + NvmapKind_C32_MS8_MS16_2CRA=0xe5, + NvmapKind_C64_2C=0xe6, + NvmapKind_C64_2CBR=0xe7, + NvmapKind_C64_2CBA=0xe8, + NvmapKind_C64_2CRA=0xe9, + NvmapKind_C64_2BRA=0xea, + NvmapKind_C64_MS2_2C=0xeb, + NvmapKind_C64_MS2_2CBR=0xeC, + NvmapKind_C64_MS4_2C=0xed, + NvmapKind_C64_MS4_2CBR=0xee, + NvmapKind_C64_MS4_2CBA=0xef, + NvmapKind_C64_MS4_2CRA=0xf0, + NvmapKind_C64_MS4_2BRA=0xf1, + NvmapKind_C64_MS8_MS16_2C=0xf2, + NvmapKind_C64_MS8_MS16_2CRA=0xf3, + NvmapKind_C128_2C=0xf4, + NvmapKind_C128_2CR=0xf5, + NvmapKind_C128_MS2_2C=0xf6, + NvmapKind_C128_MS2_2CR=0xf7, + NvmapKind_C128_MS4_2C=0xf8, + NvmapKind_C128_MS4_2CR=0xf9, + NvmapKind_C128_MS8_MS16_2C=0xfa, + NvmapKind_C128_MS8_MS16_2CR=0xfb, + NvmapKind_X8C24=0xfC, + NvmapKind_PitchNoSwizzle=0xfd, + NvmapKind_Generic_16BX2=0xfe, + NvmapKind_Invalid=0xff, +} NvmapKind; + +Result nvmapInit(); +Result nvmapExit(); + +Result nvmapCreate(Nvmap* m, size_t size, u32 align, NvmapKind kind); +Result nvmapCreateRw(Nvmap* m, size_t size, u32 align, NvmapKind kind); +void nvmapFree(Nvmap* m); + +void* nvmapGetAddr(Nvmap* m); diff --git a/nx/source/display/nvgfx.c b/nx/source/display/nvgfx.c index c3649580..3f759f67 100644 --- a/nx/source/display/nvgfx.c +++ b/nx/source/display/nvgfx.c @@ -7,8 +7,8 @@ #include "services/nv.h" #include "display/binder.h" #include "display/buffer_producer.h" -#include "display/nvioctl.h" #include "display/nvgfx.h" +#include "nvidia/ioctl.h" //#include "nvgfx_gpu_gpfifo_data0_bin.h" @@ -30,7 +30,7 @@ static Handle g_nvgfx_nvhostctrl_eventhandle = INVALID_HANDLE; static Handle g_nvgfx_nvhostctrlgpu_event2 = INVALID_HANDLE; static Handle g_nvgfx_nvhostgpu_event3 = INVALID_HANDLE; -static gpu_characteristics g_nvgfx_gpu_characteristics; +static nvioctl_gpu_characteristics g_nvgfx_gpu_characteristics; static u64 g_nvgfx_nvhostasgpu_allocspace_offset; static u32 g_nvgfx_tpcmasks[24>>2]; static u32 g_nvgfx_zcullctxsize; @@ -124,7 +124,7 @@ Result nvgfxInitialize(void) { memset(nvmap_objs, 0, sizeof(nvmap_objs)); - memset(&g_nvgfx_gpu_characteristics, 0, sizeof(gpu_characteristics)); + memset(&g_nvgfx_gpu_characteristics, 0, sizeof(nvioctl_gpu_characteristics)); memset(g_nvgfx_tpcmasks, 0, sizeof(g_nvgfx_tpcmasks)); memset(g_nvgfx_zcullinfo, 0, sizeof(g_nvgfx_zcullinfo)); memset(g_nvgfx_nvhostasgpu_varegions, 0, sizeof(g_nvgfx_nvhostasgpu_varegions)); diff --git a/nx/source/nvidia/ioctl/channel.c b/nx/source/nvidia/ioctl/channel.c index d958e541..ebe81cc6 100644 --- a/nx/source/nvidia/ioctl/channel.c +++ b/nx/source/nvidia/ioctl/channel.c @@ -2,8 +2,7 @@ #include "types.h" #include "result.h" #include "services/nv.h" -#include "display/ioctl.h" -#include "display/nvioctl.h" +#include "nvidia/ioctl.h" Result nvioctlChannel_SetNvmapFd(u32 fd, u32 nvmap_fd) { struct { diff --git a/nx/source/nvidia/ioctl/nvhost-as-gpu.c b/nx/source/nvidia/ioctl/nvhost-as-gpu.c index 90b27150..cf54dcc1 100644 --- a/nx/source/nvidia/ioctl/nvhost-as-gpu.c +++ b/nx/source/nvidia/ioctl/nvhost-as-gpu.c @@ -2,8 +2,7 @@ #include "types.h" #include "result.h" #include "services/nv.h" -#include "display/ioctl.h" -#include "display/nvioctl.h" +#include "nvidia/ioctl.h" Result nvioctlNvhostAsGpu_BindChannel(u32 fd, u32 channel_fd) { struct { diff --git a/nx/source/nvidia/ioctl/nvhost-ctrl-gpu.c b/nx/source/nvidia/ioctl/nvhost-ctrl-gpu.c index 39adbfb8..cd5ab979 100644 --- a/nx/source/nvidia/ioctl/nvhost-ctrl-gpu.c +++ b/nx/source/nvidia/ioctl/nvhost-ctrl-gpu.c @@ -2,8 +2,7 @@ #include "types.h" #include "result.h" #include "services/nv.h" -#include "display/ioctl.h" -#include "display/nvioctl.h" +#include "nvidia/ioctl.h" Result nvioctlNvhostCtrlGpu_ZCullGetCtxSize(u32 fd, u32 *out) { Result rc = 0; @@ -41,23 +40,23 @@ Result nvioctlNvhostCtrlGpu_ZCullGetInfo(u32 fd, u32 out[40>>2]) { return rc; } -Result nvioctlNvhostCtrlGpu_GetCharacteristics(u32 fd, gpu_characteristics *out) { +Result nvioctlNvhostCtrlGpu_GetCharacteristics(u32 fd, nvioctl_gpu_characteristics *out) { Result rc = 0; struct { __nv_in u64 gc_buf_size; // must not be NULL, but gets overwritten with 0xA0=max_size __nv_in u64 gc_buf_addr; // ignored, but must not be NULL - __nv_out gpu_characteristics gc; + __nv_out nvioctl_gpu_characteristics gc; } data; memset(&data, 0, sizeof(data)); - data.gc_buf_size = sizeof(gpu_characteristics); + data.gc_buf_size = sizeof(nvioctl_gpu_characteristics); data.gc_buf_addr = 1; rc = nvIoctl(fd, _NV_IOWR(0x47, 0x05, data), &data); if (R_SUCCEEDED(rc)) { - memcpy(out, &data.gc, sizeof(gpu_characteristics)); + memcpy(out, &data.gc, sizeof(nvioctl_gpu_characteristics)); } return rc; diff --git a/nx/source/nvidia/ioctl/nvhost-ctrl.c b/nx/source/nvidia/ioctl/nvhost-ctrl.c index d78db31c..77be6d36 100644 --- a/nx/source/nvidia/ioctl/nvhost-ctrl.c +++ b/nx/source/nvidia/ioctl/nvhost-ctrl.c @@ -2,8 +2,7 @@ #include "types.h" #include "result.h" #include "services/nv.h" -#include "display/ioctl.h" -#include "display/nvioctl.h" +#include "nvidia/ioctl.h" Result nvioctlNvhostCtrl_EventSignal(u32 fd, u32 event_id) { struct { diff --git a/nx/source/nvidia/nvmap.c b/nx/source/nvidia/nvmap.c new file mode 100644 index 00000000..724be364 --- /dev/null +++ b/nx/source/nvidia/nvmap.c @@ -0,0 +1,67 @@ +#include +#include "types.h" +#include "result.h" +#include "services/nv.h" +#include "nvidia/ioctl.h" +#include "nvidia/nvmap.h" + +static u32 g_nvmap_fd; + +Result nvmapInit() { + return nvOpen(&g_nvmap_fd, "/dev/nvmap"); +} + +Result nvmapExit() { + return nvClose(g_nvmap_fd); +} + +static Result _nvmapCreate(Nvmap* m, size_t size, u32 flags, u32 align, NvmapKind kind) +{ + Result rc; + + m->size = size; + m->fd = -1; + m->ptr = memalign(size, align); + + if (m->ptr == NULL) + return MAKERESULT(Module_Libnx, LibnxError_OutOfMemory); + + rc = nvioctlNvmap_Create(g_nvmap_fd, size, &m->fd); + + if (R_SUCCEEDED(rc)) { + rc = nvioctlNvmap_Alloc(g_nvmap_fd, m->fd, 0, flags, align, kind, m->ptr); + + if (R_FAILED(rc)) { + nvClose(m->fd); + m->fd = -1; + } + } + + if (R_FAILED(rc)) { + free(m->ptr); + m->ptr = NULL; + } + + return rc; +} + +Result nvmapCreate(Nvmap* m, size_t size, u32 align, NvmapKind kind) { + return _nvmapCreate(m, size, 0, align, kind); +} + +Result nvmapCreateRw(Nvmap* m, size_t size, u32 align, NvmapKind kind) { + return _nvmapCreate(m, size, NvmapFlags_Writable, align, kind); +} + +void nvmapFree(Nvmap* m) +{ + free(m->ptr); + m->ptr = NULL; + + nvClose(m->fd); + m->fd = -1; +} + +void* nvmapGetAddr(Nvmap* m) { + return m->ptr; +} diff --git a/nx/source/services/nv.c b/nx/source/services/nv.c index e62d27cf..0b4e1ac9 100644 --- a/nx/source/services/nv.c +++ b/nx/source/services/nv.c @@ -3,7 +3,7 @@ #include "result.h" #include "kernel/ipc.h" #include "services/applet.h" -#include "display/ioctl.h" +#include "nvidia/ioctl.h" #include "services/nv.h" #include "services/sm.h" #include "kernel/tmem.h"