From c5c7a4c739c11193c195c51b0a3f48c07f58a6a8 Mon Sep 17 00:00:00 2001 From: plutoo Date: Sun, 11 Mar 2018 21:56:46 +0100 Subject: [PATCH] Change code style --- nx/include/switch/nvidia/address_space.h | 14 +++---- nx/include/switch/nvidia/buffer.h | 14 +++---- nx/include/switch/nvidia/channel.h | 8 ++-- nx/include/switch/nvidia/gpu/3d_ctx.h | 6 +-- nx/include/switch/nvidia/gpu/error_notifier.h | 4 +- nx/include/switch/nvidia/gpu/gpfifo.h | 6 +-- nx/include/switch/nvidia/gpu/gpu.h | 2 +- nx/include/switch/nvidia/gpu/zcull_ctx.h | 4 +- nx/include/switch/nvidia/info.h | 6 +-- nx/source/nvidia/address_space.c | 18 ++++---- nx/source/nvidia/buffer.c | 22 +++++----- nx/source/nvidia/channel.c | 12 +++--- nx/source/nvidia/gpu/3d_ctx.c | 4 +- nx/source/nvidia/gpu/error_notifier.c | 8 ++-- nx/source/nvidia/gpu/gpfifo.c | 6 +-- nx/source/nvidia/gpu/gpu.c | 42 +++++++++---------- nx/source/nvidia/gpu/zcull_ctx.c | 12 +++--- nx/source/nvidia/info.c | 8 ++-- 18 files changed, 98 insertions(+), 98 deletions(-) diff --git a/nx/include/switch/nvidia/address_space.h b/nx/include/switch/nvidia/address_space.h index 6ee2955f..fc1a4fff 100644 --- a/nx/include/switch/nvidia/address_space.h +++ b/nx/include/switch/nvidia/address_space.h @@ -11,14 +11,14 @@ typedef enum { typedef u64 iova_t; -Result nvasCreate(NvAddressSpace* a); -void nvasClose(NvAddressSpace* a); +Result nvAddressSpaceCreate(NvAddressSpace* a); +void nvAddressSpaceClose(NvAddressSpace* a); -Result nvasReserveAlign(NvAddressSpace* a, NvPageSize align, u32 pages, NvPageSize page_sz, iova_t* iova_out); -Result nvasReserveAtFixedAddr(NvAddressSpace* a, iova_t addr, u32 pages, NvPageSize page_sz); -Result nvasReserveFull(NvAddressSpace* a); +Result nvAddressSpaceReserveAlign(NvAddressSpace* a, NvPageSize align, u32 pages, NvPageSize page_sz, iova_t* iova_out); +Result nvAddressSpaceReserveAtFixedAddr(NvAddressSpace* a, iova_t addr, u32 pages, NvPageSize page_sz); +Result nvAddressSpaceReserveFull(NvAddressSpace* a); -Result nvasMapBuffer(NvAddressSpace* a, NvBuffer* buffer, NvBufferKind kind, iova_t* iova_out); +Result nvAddressSpaceMapBuffer(NvAddressSpace* a, NvBuffer* buffer, NvBufferKind kind, iova_t* iova_out); struct NvChannel; -Result nvasBindToChannel(NvAddressSpace* a, struct NvChannel* channel); +Result nvAddressSpaceBindToChannel(NvAddressSpace* a, struct NvChannel* channel); diff --git a/nx/include/switch/nvidia/buffer.h b/nx/include/switch/nvidia/buffer.h index ca8bbe66..0985bd42 100644 --- a/nx/include/switch/nvidia/buffer.h +++ b/nx/include/switch/nvidia/buffer.h @@ -249,12 +249,12 @@ typedef struct { bool has_init; } NvBuffer; -Result nvbufInit(void); -u32 nvbufGetNvmapFd(void); -void nvbufExit(void); +Result nvBufferInit(void); +u32 nvBufferGetNvmapFd(void); +void nvBufferExit(void); -Result nvbufCreate(NvBuffer* m, size_t size, u32 align, NvBufferKind kind); -Result nvbufCreateRw(NvBuffer* m, size_t size, u32 align, NvBufferKind kind); -void nvbufFree(NvBuffer* m); +Result nvBufferCreate(NvBuffer* m, size_t size, u32 align, NvBufferKind kind); +Result nvBufferCreateRw(NvBuffer* m, size_t size, u32 align, NvBufferKind kind); +void nvBufferFree(NvBuffer* m); -void* nvbufGetAddr(NvBuffer* m); +void* nvBufferGetAddr(NvBuffer* m); diff --git a/nx/include/switch/nvidia/channel.h b/nx/include/switch/nvidia/channel.h index 16b3b155..10414ad9 100644 --- a/nx/include/switch/nvidia/channel.h +++ b/nx/include/switch/nvidia/channel.h @@ -5,8 +5,8 @@ typedef struct NvChannel { bool has_init; } NvChannel; -Result nvchannelCreate(NvChannel* c, const char* dev); -void nvchannelClose(NvChannel* c); +Result nvChannelCreate(NvChannel* c, const char* dev); +void nvChannelClose(NvChannel* c); -Result nvchannelSetPriority(NvChannel* c, NvChannelPriority prio); -Result nvchannelSetNvmapFd(NvChannel* c); +Result nvChannelSetPriority(NvChannel* c, NvChannelPriority prio); +Result nvChannelSetNvmapFd(NvChannel* c); diff --git a/nx/include/switch/nvidia/gpu/3d_ctx.h b/nx/include/switch/nvidia/gpu/3d_ctx.h index 04989f93..73bf3289 100644 --- a/nx/include/switch/nvidia/gpu/3d_ctx.h +++ b/nx/include/switch/nvidia/gpu/3d_ctx.h @@ -3,7 +3,7 @@ typedef struct NvGpu NvGpu; typedef struct { NvGpu* parent; u64 obj_id; -} Nv3dContext; +} Nv3DContext; -Result nv3dCreate(Nv3dContext* t, NvGpu* parent); -void nv3dClose(Nv3dContext* t); +Result nv3DContextCreate(Nv3DContext* t, NvGpu* parent); +void nv3DContextClose(Nv3DContext* t); diff --git a/nx/include/switch/nvidia/gpu/error_notifier.h b/nx/include/switch/nvidia/gpu/error_notifier.h index e8e2f299..42c375b4 100644 --- a/nx/include/switch/nvidia/gpu/error_notifier.h +++ b/nx/include/switch/nvidia/gpu/error_notifier.h @@ -6,5 +6,5 @@ typedef struct { bool has_init; } NvErrorNotifier; -Result nverrCreate(NvErrorNotifier* t, NvGpu* parent); -void nverrClose(NvErrorNotifier* t); +Result nvErrorNotifierCreate(NvErrorNotifier* t, NvGpu* parent); +void nvErrorNotifierClose(NvErrorNotifier* t); diff --git a/nx/include/switch/nvidia/gpu/gpfifo.h b/nx/include/switch/nvidia/gpu/gpfifo.h index 5097bf39..89a972ff 100644 --- a/nx/include/switch/nvidia/gpu/gpfifo.h +++ b/nx/include/switch/nvidia/gpu/gpfifo.h @@ -3,10 +3,10 @@ typedef struct { nvioctl_fence fifo_fence; } NvGpfifo; -Result nvfifoCreate(NvGpfifo* f, NvChannel* parent); -void nvfifoClose(NvGpfifo* f); +Result nvGpfifoCreate(NvGpfifo* f, NvChannel* parent); +void nvGpfifoClose(NvGpfifo* f); #define NV_MAKE_GPFIFO_ENTRY(iova, size) \ ((iova) | (((u64)(size)) << 42)) -Result nvfifoSubmit(NvGpfifo* f, NvCmdList* cmd_list, NvFence* fence_out); +Result nvGpfifoSubmit(NvGpfifo* f, NvCmdList* cmd_list, NvFence* fence_out); diff --git a/nx/include/switch/nvidia/gpu/gpu.h b/nx/include/switch/nvidia/gpu/gpu.h index a549e74f..5fc3040c 100644 --- a/nx/include/switch/nvidia/gpu/gpu.h +++ b/nx/include/switch/nvidia/gpu/gpu.h @@ -3,7 +3,7 @@ typedef struct NvGpu { NvChannel gpu_channel; NvGpfifo gpfifo; NvZcullContext zcull_ctx; - Nv3dContext _3d_ctx; + Nv3DContext _3d_ctx; NvErrorNotifier error_notifier; } NvGpu; diff --git a/nx/include/switch/nvidia/gpu/zcull_ctx.h b/nx/include/switch/nvidia/gpu/zcull_ctx.h index a27fda49..77ab17ec 100644 --- a/nx/include/switch/nvidia/gpu/zcull_ctx.h +++ b/nx/include/switch/nvidia/gpu/zcull_ctx.h @@ -5,5 +5,5 @@ typedef struct { NvBuffer ctx_buf; } NvZcullContext; -Result nvzcullCreate(NvZcullContext* z, NvGpu* parent); -void nvzcullClose(NvZcullContext* z); +Result nvZcullContextCreate(NvZcullContext* z, NvGpu* parent); +void nvZcullContextClose(NvZcullContext* z); diff --git a/nx/include/switch/nvidia/info.h b/nx/include/switch/nvidia/info.h index 02bdf99b..a2339651 100644 --- a/nx/include/switch/nvidia/info.h +++ b/nx/include/switch/nvidia/info.h @@ -1,4 +1,4 @@ -Result nvinfoInit(); -void nvinfoExit(); +Result nvInfoInit(); +void nvInfoExit(); -u32 nvinfoGetZcullCtxSize(); +u32 nvInfoGetZcullCtxSize(); diff --git a/nx/source/nvidia/address_space.c b/nx/source/nvidia/address_space.c index af245f23..7b35280e 100644 --- a/nx/source/nvidia/address_space.c +++ b/nx/source/nvidia/address_space.c @@ -1,6 +1,6 @@ #include -Result nvasCreate(NvAddressSpace* a) +Result nvAddressSpaceCreate(NvAddressSpace* a) { Result rc; @@ -15,12 +15,12 @@ Result nvasCreate(NvAddressSpace* a) rc = nvioctlNvhostAsGpu_InitializeEx(a->fd, 1, 0x10000); if (R_FAILED(rc)) - nvasClose(a); + nvAddressSpaceClose(a); return rc; } -void nvasClose(NvAddressSpace* a) +void nvAddressSpaceClose(NvAddressSpace* a) { if (!a->has_init) return; @@ -31,24 +31,24 @@ void nvasClose(NvAddressSpace* a) a->fd = -1; } -Result nvasReserveAlign(NvAddressSpace* a, NvPageSize align, u32 pages, NvPageSize page_sz, iova_t* iova_out) { +Result nvAddressSpaceReserveAlign(NvAddressSpace* a, NvPageSize align, u32 pages, NvPageSize page_sz, iova_t* iova_out) { return nvioctlNvhostAsGpu_AllocSpace(a->fd, pages, page_sz, 0, align, iova_out); } -Result nvasReserveAtFixedAddr(NvAddressSpace* a, iova_t addr, u32 pages, NvPageSize page_sz) { +Result nvAddressSpaceReserveAtFixedAddr(NvAddressSpace* a, iova_t addr, u32 pages, NvPageSize page_sz) { return nvioctlNvhostAsGpu_AllocSpace(a->fd, pages, page_sz, 1, addr, NULL); } -Result nvasReserveFull(NvAddressSpace* a) { - return nvasReserveAlign(a, NvPageSize_64K, 0x10000, NvPageSize_64K, NULL); +Result nvAddressSpaceReserveFull(NvAddressSpace* a) { + return nvAddressSpaceReserveAlign(a, NvPageSize_64K, 0x10000, NvPageSize_64K, NULL); } -Result nvasMapBuffer(NvAddressSpace* a, NvBuffer* buffer, NvBufferKind kind, iova_t* iova_out) { +Result nvAddressSpaceMapBuffer(NvAddressSpace* a, NvBuffer* buffer, NvBufferKind kind, iova_t* iova_out) { // TODO: What is flag==4? return nvioctlNvhostAsGpu_MapBufferEx( a->fd, NvMapBufferFlags_IsCachable, kind, buffer->fd, 0x10000, 0, 0, 0, iova_out); } -Result nvasBindToChannel(NvAddressSpace* a, NvChannel* channel) { +Result nvAddressSpaceBindToChannel(NvAddressSpace* a, NvChannel* channel) { return nvioctlNvhostAsGpu_BindChannel(a->fd, channel->fd); } diff --git a/nx/source/nvidia/buffer.c b/nx/source/nvidia/buffer.c index 39aa22e0..fda0e744 100644 --- a/nx/source/nvidia/buffer.c +++ b/nx/source/nvidia/buffer.c @@ -9,7 +9,7 @@ static u32 g_nvmap_fd = -1; static u64 g_refCnt; -Result nvbufInit(void) +Result nvBufferInit(void) { Result rc; @@ -24,7 +24,7 @@ Result nvbufInit(void) return rc; } -void nvbufExit(void) +void nvBufferExit(void) { if (atomicDecrement64(&g_refCnt) == 0) { @@ -35,11 +35,11 @@ void nvbufExit(void) } } -u32 nvbufGetNvmapFd(void) { +u32 nvBufferGetNvmapFd(void) { return g_nvmap_fd; } -static Result _nvbufCreate(NvBuffer* m, size_t size, u32 flags, u32 align, NvBufferKind kind) +static Result _nvBufferCreate(NvBuffer* m, size_t size, u32 flags, u32 align, NvBufferKind kind) { Result rc; @@ -63,20 +63,20 @@ static Result _nvbufCreate(NvBuffer* m, size_t size, u32 flags, u32 align, NvBuf rc = nvioctlNvmap_Alloc(g_nvmap_fd, m->fd, 0, flags | NvBufferFlags_Nintendo, align, kind, m->ptr); if (R_FAILED(rc)) - nvbufFree(m); + nvBufferFree(m); return rc; } -Result nvbufCreate(NvBuffer* m, size_t size, u32 align, NvBufferKind kind) { - return _nvbufCreate(m, size, 0, align, kind); +Result nvBufferCreate(NvBuffer* m, size_t size, u32 align, NvBufferKind kind) { + return _nvBufferCreate(m, size, 0, align, kind); } -Result nvbufCreateRw(NvBuffer* m, size_t size, u32 align, NvBufferKind kind) { - return _nvbufCreate(m, size, NvBufferFlags_Writable, align, kind); +Result nvBufferCreateRw(NvBuffer* m, size_t size, u32 align, NvBufferKind kind) { + return _nvBufferCreate(m, size, NvBufferFlags_Writable, align, kind); } -void nvbufFree(NvBuffer* m) +void nvBufferFree(NvBuffer* m) { if (!m->has_init) return; @@ -90,6 +90,6 @@ void nvbufFree(NvBuffer* m) m->fd = -1; } -void* nvbufGetAddr(NvBuffer* m) { +void* nvBufferGetAddr(NvBuffer* m) { return m->ptr; } diff --git a/nx/source/nvidia/channel.c b/nx/source/nvidia/channel.c index be1e6740..9af308f3 100644 --- a/nx/source/nvidia/channel.c +++ b/nx/source/nvidia/channel.c @@ -1,6 +1,6 @@ #include -Result nvchannelCreate(NvChannel* c, const char* dev) +Result nvChannelCreate(NvChannel* c, const char* dev) { Result rc; @@ -12,12 +12,12 @@ Result nvchannelCreate(NvChannel* c, const char* dev) c->fd = -1; if (R_FAILED(rc)) - nvchannelClose(c); + nvChannelClose(c); return rc; } -void nvchannelClose(NvChannel* c) +void nvChannelClose(NvChannel* c) { if (!c->has_init) return; @@ -28,10 +28,10 @@ void nvchannelClose(NvChannel* c) c->fd = -1; } -Result nvchannelSetPriority(NvChannel* c, NvChannelPriority prio) { +Result nvChannelSetPriority(NvChannel* c, NvChannelPriority prio) { return nvioctlChannel_SetPriority(c->fd, prio); } -Result nvchannelSetNvmapFd(NvChannel* c) { - return nvioctlChannel_SetNvmapFd(c->fd, nvbufGetNvmapFd()); +Result nvChannelSetNvmapFd(NvChannel* c) { + return nvioctlChannel_SetNvmapFd(c->fd, nvBufferGetNvmapFd()); } diff --git a/nx/source/nvidia/gpu/3d_ctx.c b/nx/source/nvidia/gpu/3d_ctx.c index 966dcb2b..c7bb5c45 100644 --- a/nx/source/nvidia/gpu/3d_ctx.c +++ b/nx/source/nvidia/gpu/3d_ctx.c @@ -1,11 +1,11 @@ #include -Result nv3dCreate(Nv3dContext* t, NvGpu* parent) +Result nv3DContextCreate(Nv3DContext* t, NvGpu* parent) { t->parent = parent; return nvioctlChannel_AllocObjCtx(parent->gpu_channel.fd, NvClassNumber_3D, 0, &t->obj_id); } -void nv3dClose(Nv3dContext* t) { +void nv3DContextClose(Nv3DContext* t) { // Empty } diff --git a/nx/source/nvidia/gpu/error_notifier.c b/nx/source/nvidia/gpu/error_notifier.c index bcb72d16..e3e87ce1 100644 --- a/nx/source/nvidia/gpu/error_notifier.c +++ b/nx/source/nvidia/gpu/error_notifier.c @@ -1,6 +1,6 @@ #include -Result nverrCreate(NvErrorNotifier* t, NvGpu* parent) +Result nvErrorNotifierCreate(NvErrorNotifier* t, NvGpu* parent) { Result rc; Handle handle; @@ -20,7 +20,7 @@ Result nverrCreate(NvErrorNotifier* t, NvGpu* parent) return rc; } -void nverrClose(NvErrorNotifier* t) +void nvErrorNotifierClose(NvErrorNotifier* t) { if (!t->has_init) return; @@ -29,10 +29,10 @@ void nverrClose(NvErrorNotifier* t) eventClose(&t->event); } -Result nverrWait(NvErrorNotifier* t, u64 timeout) { +Result nvErrorNotifierWait(NvErrorNotifier* t, u64 timeout) { return eventWait(&t->event, timeout); } -Result nverrGetError(NvErrorNotifier* t, NvError* out) { +Result nvErrorNotifierGetError(NvErrorNotifier* t, NvError* out) { return nvioctlChannel_GetErrorNotification(t->parent->gpu_channel.fd, out); } diff --git a/nx/source/nvidia/gpu/gpfifo.c b/nx/source/nvidia/gpu/gpfifo.c index 577f85e8..007d9ce8 100644 --- a/nx/source/nvidia/gpu/gpfifo.c +++ b/nx/source/nvidia/gpu/gpfifo.c @@ -2,7 +2,7 @@ #define DEFAULT_FIFO_ENTRIES 0x800 -Result nvfifoCreate(NvGpfifo* f, NvChannel* parent) +Result nvGpfifoCreate(NvGpfifo* f, NvChannel* parent) { f->parent = parent; @@ -10,11 +10,11 @@ Result nvfifoCreate(NvGpfifo* f, NvChannel* parent) parent->fd, DEFAULT_FIFO_ENTRIES, 1, 0, 0, 0, 0, &f->fifo_fence); } -void nvfifoClose(NvGpfifo* f) { +void nvGpfifoClose(NvGpfifo* f) { /**/ } -Result nvfifoSubmit(NvGpfifo* f, NvCmdList* cmd_list, NvFence* fence_out) +Result nvGpfifoSubmit(NvGpfifo* f, NvCmdList* cmd_list, NvFence* fence_out) { Result rc; nvioctl_gpfifo_entry ent; diff --git a/nx/source/nvidia/gpu/gpu.c b/nx/source/nvidia/gpu/gpu.c index 093f67b6..2f82633a 100644 --- a/nx/source/nvidia/gpu/gpu.c +++ b/nx/source/nvidia/gpu/gpu.c @@ -4,42 +4,42 @@ Result nvgpuCreate(NvGpu* g) { Result rc; - if (R_FAILED(nvinfoInit())) + if (R_FAILED(nvInfoInit())) return MAKERESULT(Module_Libnx, LibnxError_NvinfoFailedToInitialize); - if (R_FAILED(nvbufInit())) { - nvinfoExit(); + if (R_FAILED(nvBufferInit())) { + nvInfoExit(); return MAKERESULT(Module_Libnx, LibnxError_NvbufFailedToInitialize); } - rc = nvchannelCreate(&g->gpu_channel, "/dev/nvhost-gpu"); + rc = nvChannelCreate(&g->gpu_channel, "/dev/nvhost-gpu"); if (R_SUCCEEDED(rc)) - rc = nvasCreate(&g->addr_space); + rc = nvAddressSpaceCreate(&g->addr_space); if (R_SUCCEEDED(rc)) - rc = nvasReserveFull(&g->addr_space); + rc = nvAddressSpaceReserveFull(&g->addr_space); if (R_SUCCEEDED(rc)) - rc = nvasBindToChannel(&g->addr_space, &g->gpu_channel); + rc = nvAddressSpaceBindToChannel(&g->addr_space, &g->gpu_channel); if (R_SUCCEEDED(rc)) - rc = nvchannelSetNvmapFd(&g->gpu_channel); + rc = nvChannelSetNvmapFd(&g->gpu_channel); if (R_SUCCEEDED(rc)) - rc = nvfifoCreate(&g->gpfifo, &g->gpu_channel); + rc = nvGpfifoCreate(&g->gpfifo, &g->gpu_channel); if (R_SUCCEEDED(rc)) - rc = nv3dCreate(&g->_3d_ctx, g); + rc = nv3DContextCreate(&g->_3d_ctx, g); if (R_SUCCEEDED(rc)) - rc = nverrCreate(&g->error_notifier, g); + rc = nvErrorNotifierCreate(&g->error_notifier, g); if (R_SUCCEEDED(rc)) - rc = nvchannelSetPriority(&g->gpu_channel, NvChannelPriority_Medium); + rc = nvChannelSetPriority(&g->gpu_channel, NvChannelPriority_Medium); if (R_SUCCEEDED(rc)) - rc = nvzcullCreate(&g->zcull_ctx, g); + rc = nvZcullContextCreate(&g->zcull_ctx, g); if (R_FAILED(rc)) nvgpuClose(g); @@ -49,13 +49,13 @@ Result nvgpuCreate(NvGpu* g) void nvgpuClose(NvGpu* g) { - nvbufExit(); - nvinfoExit(); + nvBufferExit(); + nvInfoExit(); - nverrClose(&g->error_notifier); - nvzcullClose(&g->zcull_ctx); - nv3dClose(&g->_3d_ctx); - nvfifoClose(&g->gpfifo); - nvasClose(&g->addr_space); - nvchannelClose(&g->gpu_channel); + nvErrorNotifierClose(&g->error_notifier); + nvZcullContextClose(&g->zcull_ctx); + nv3DContextClose(&g->_3d_ctx); + nvGpfifoClose(&g->gpfifo); + nvAddressSpaceClose(&g->addr_space); + nvChannelClose(&g->gpu_channel); } diff --git a/nx/source/nvidia/gpu/zcull_ctx.c b/nx/source/nvidia/gpu/zcull_ctx.c index 4776e4fe..82fd3fb6 100644 --- a/nx/source/nvidia/gpu/zcull_ctx.c +++ b/nx/source/nvidia/gpu/zcull_ctx.c @@ -1,20 +1,20 @@ #include -Result nvzcullCreate(NvZcullContext* z, NvGpu* parent) +Result nvZcullContextCreate(NvZcullContext* z, NvGpu* parent) { Result rc; z->parent = parent; - rc = nvbufCreateRw(&z->ctx_buf, nvinfoGetZcullCtxSize(), 0x20000, NvBufferKind_Pitch); + rc = nvBufferCreateRw(&z->ctx_buf, nvInfoGetZcullCtxSize(), 0x20000, NvBufferKind_Pitch); iova_t iova_out; if (R_SUCCEEDED(rc)) - rc = nvasMapBuffer(&parent->addr_space, &z->ctx_buf, NvBufferKind_Pitch, &iova_out); + rc = nvAddressSpaceMapBuffer(&parent->addr_space, &z->ctx_buf, NvBufferKind_Pitch, &iova_out); if (R_SUCCEEDED(rc)) - rc = nvasMapBuffer(&parent->addr_space, &z->ctx_buf, NvBufferKind_Generic_16BX2, /*&iova_out*/ NULL); + rc = nvAddressSpaceMapBuffer(&parent->addr_space, &z->ctx_buf, NvBufferKind_Generic_16BX2, /*&iova_out*/ NULL); if (R_SUCCEEDED(rc)) rc = nvioctlChannel_ZCullBind(parent->gpu_channel.fd, iova_out, NvZcullConfig_SeparateBuffer); @@ -22,7 +22,7 @@ Result nvzcullCreate(NvZcullContext* z, NvGpu* parent) return rc; } -void nvzcullClose(NvZcullContext* z) { +void nvZcullContextClose(NvZcullContext* z) { // TODO: Unmap z->ctx_buf from parent->addr_space? - nvbufFree(&z->ctx_buf); + nvBufferFree(&z->ctx_buf); } diff --git a/nx/source/nvidia/info.c b/nx/source/nvidia/info.c index 683770a6..34f0ea24 100644 --- a/nx/source/nvidia/info.c +++ b/nx/source/nvidia/info.c @@ -6,7 +6,7 @@ static u64 g_refCnt; static nvioctl_gpu_characteristics g_gpu_characteristics; static u32 g_zcull_ctx_size; -Result nvinfoInit() +Result nvInfoInit() { Result rc; @@ -25,12 +25,12 @@ Result nvinfoInit() rc = nvioctlNvhostCtrlGpu_ZCullGetCtxSize(g_ctrlgpu_fd, &g_zcull_ctx_size); if (R_FAILED(rc)) - nvinfoExit(); + nvInfoExit(); return rc; } -void nvinfoExit() +void nvInfoExit() { if (atomicDecrement64(&g_refCnt) == 0) { @@ -41,6 +41,6 @@ void nvinfoExit() } } -u32 nvinfoGetZcullCtxSize() { +u32 nvInfoGetZcullCtxSize() { return g_zcull_ctx_size; }