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ClearBuffers not yet working. SAD!

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This commit is contained in:
plutooo 2018-03-25 20:33:23 +02:00
parent 8fc8d42d61
commit 9e1d4dbb67
4 changed files with 52 additions and 1 deletions
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1
nx/include/switch.h
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@ -69,6 +69,7 @@ extern "C" {
#include "switch/nvidia/gpu/error_notifier.h"
#include "switch/nvidia/gpu/gpu.h"
#include "switch/nvidia/cmds/common.h"
#include "switch/nvidia/cmds/3d.h"
#include "switch/runtime/env.h"

17
nx/include/switch/nvidia/cmds/3d.h
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@ -1,3 +1,18 @@
enum {
NvReg3D_MultisampleEnable = 0x54d
NvReg3D_ClearColor = 0x360,
NvReg3D_ScreenScissorHorizontal = 0x3fd,
NvReg3D_ScreenScissorVertical = 0x3fe,
NvReg3D_RenderTargetControl = 0x487,
NvReg3D_RenderTargetNAddr = 0x200,
NvReg3D_RenderTargetNHorizontal = 0x202,
NvReg3D_RenderTargetNVertical = 0x203,
NvReg3D_RenderTargetNFormat = 0x204,
NvReg3D_RenderTargetNTileMode = 0x205,
NvReg3D_RenderTargetNArrayMode = 0x206,
NvReg3D_RenderTargetNLayerStride = 0x207,
NvReg3D_RenderTargetNBaseLayer = 0x208,
NvReg3D_MultisampleEnable = 0x54d,
NvReg3D_ClearBufferTrigger = 0x674,
};
void nvCmdsClearColor(NvCmdList* cmds, float colors[4]);

5
nx/include/switch/nvidia/gpu/cmd_list.h
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@ -29,3 +29,8 @@ u32* nvCmdListInsert(NvCmdList* c, size_t num_cmds);
#define NvIncrOnce(subc, reg, ...) \
(0xA0000000 | ((reg) | ((subc) << 13) | ((sizeof((u32[]) { __VA_ARGS__ })) << 16))), __VA_ARGS__
static inline u32 f2i(float f) {
#pragma GCC diagnostic ignored "-Wstrict-aliasing"
return *(u32*) &f;
}

30
nx/source/nvidia/cmds/3d.c
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@ -1,2 +1,32 @@
#include <switch.h>
#include <string.h>
void nvCmdsClearBuffer(
NvCmdList* cmds, NvBuffer* buf, u32 width, u32 height, float colors[4])
{
NvCmd(cmds, NvIncr(0, NvReg3D_ClearColor,
f2i(colors[0]), f2i(colors[1]), f2i(colors[2]), f2i(colors[3])));
NvCmd(cmds, NvIncr(0, NvReg3D_ScreenScissorHorizontal,
0 | (0x100 << 16), 0 | (0x100 << 16)));
NvCmd(cmds, NvImm(0, NvReg3D_RenderTargetControl, 1)); // bit0 probably enables RT #0
iova_t gpu_addr = nvBufferGetGpuAddr(buf);
NvCmd(cmds, NvIncr(NvReg3D_RenderTargetNAddr + 0x10*0,
gpu_addr >> 32, gpu_addr,
width, height,
0xfe /* Format */,
0x1000 /* TileMode */,
1 /* ArrayMode */,
0 /* Stride */,
0 /* BaseLayer */
));
int z;
for (z=0; z<32; z++)
NvCmd(cmds, NvImm(0, NvReg3D_ClearBufferTrigger, 0x3c | (z << 10)));
/*
TODO:
IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0);
IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 0);
*/
}