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Rename nvmap->buffer

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This commit is contained in:
plutooo 2018-02-26 06:20:44 +01:00 committed by fincs
parent 04751087ca
commit 9a759c26f5
7 changed files with 277 additions and 272 deletions
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2
nx/include/switch.h
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@ -72,7 +72,7 @@ extern "C" {
#include "switch/display/nvgfx.h" #include "switch/display/nvgfx.h"
#include "switch/nvidia/ioctl.h" #include "switch/nvidia/ioctl.h"
#include "switch/nvidia/nvmap.h" #include "switch/nvidia/buffer.h"
#include "switch/nvidia/address_space.h" #include "switch/nvidia/address_space.h"
#include "switch/audio/driver.h" #include "switch/audio/driver.h"

2
nx/include/switch/nvidia/address_space.h
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@ -19,4 +19,4 @@ Result nvasReserveAlign(NvAddressSpace* a, NvPageSize align, u32 pages, NvPageSi
Result nvasReserveAtFixedAddr(NvAddressSpace* a, iova_t addr, u32 pages, NvPageSize page_sz); Result nvasReserveAtFixedAddr(NvAddressSpace* a, iova_t addr, u32 pages, NvPageSize page_sz);
Result nvasReserveFull(NvAddressSpace* a); Result nvasReserveFull(NvAddressSpace* a);
Result nvasMapBuffer(NvAddressSpace* a, Nvmap* buffer, NvmapKind kind, iova_t* iova_out); Result nvasMapBuffer(NvAddressSpace* a, NvBuffer* buffer, NvBufferKind kind, iova_t* iova_out);

258
nx/include/switch/nvidia/buffer.h Normal file
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@ -0,0 +1,258 @@
#pragma once
#include "../types.h"
typedef struct {
u32 fd;
u32 size;
void* ptr;
} NvBuffer;
typedef enum {
NvBufferFlags_Writable=1
} NvBufferFlags;
typedef enum {
NvBufferKind_PitCh=0x0,
NvBufferKind_Z16=0x1,
NvBufferKind_Z16_2C=0x2,
NvBufferKind_Z16_MS2_2C=0x3,
NvBufferKind_Z16_MS4_2C=0x4,
NvBufferKind_Z16_MS8_2C=0x5,
NvBufferKind_Z16_MS16_2C=0x6,
NvBufferKind_Z16_2Z=0x7,
NvBufferKind_Z16_MS2_2Z=0x8,
NvBufferKind_Z16_MS4_2Z=0x9,
NvBufferKind_Z16_MS8_2Z=0xa,
NvBufferKind_Z16_MS16_2Z=0xb,
NvBufferKind_Z16_4CZ=0xC,
NvBufferKind_Z16_MS2_4CZ=0xd,
NvBufferKind_Z16_MS4_4CZ=0xe,
NvBufferKind_Z16_MS8_4CZ=0xf,
NvBufferKind_Z16_MS16_4CZ=0x10,
NvBufferKind_S8Z24=0x11,
NvBufferKind_S8Z24_1Z=0x12,
NvBufferKind_S8Z24_MS2_1Z=0x13,
NvBufferKind_S8Z24_MS4_1Z=0x14,
NvBufferKind_S8Z24_MS8_1Z=0x15,
NvBufferKind_S8Z24_MS16_1Z=0x16,
NvBufferKind_S8Z24_2CZ=0x17,
NvBufferKind_S8Z24_MS2_2CZ=0x18,
NvBufferKind_S8Z24_MS4_2CZ=0x19,
NvBufferKind_S8Z24_MS8_2CZ=0x1a,
NvBufferKind_S8Z24_MS16_2CZ=0x1b,
NvBufferKind_S8Z24_2CS=0x1C,
NvBufferKind_S8Z24_MS2_2CS=0x1d,
NvBufferKind_S8Z24_MS4_2CS=0x1e,
NvBufferKind_S8Z24_MS8_2CS=0x1f,
NvBufferKind_S8Z24_MS16_2CS=0x20,
NvBufferKind_S8Z24_4CSZV=0x21,
NvBufferKind_S8Z24_MS2_4CSZV=0x22,
NvBufferKind_S8Z24_MS4_4CSZV=0x23,
NvBufferKind_S8Z24_MS8_4CSZV=0x24,
NvBufferKind_S8Z24_MS16_4CSZV=0x25,
NvBufferKind_V8Z24_MS4_VC12=0x26,
NvBufferKind_V8Z24_MS4_VC4=0x27,
NvBufferKind_V8Z24_MS8_VC8=0x28,
NvBufferKind_V8Z24_MS8_VC24=0x29,
NvBufferKind_S8=0x2a,
NvBufferKind_S8_2S=0x2b,
NvBufferKind_V8Z24_MS4_VC12_1ZV=0x2e,
NvBufferKind_V8Z24_MS4_VC4_1ZV=0x2f,
NvBufferKind_V8Z24_MS8_VC8_1ZV=0x30,
NvBufferKind_V8Z24_MS8_VC24_1ZV=0x31,
NvBufferKind_V8Z24_MS4_VC12_2CS=0x32,
NvBufferKind_V8Z24_MS4_VC4_2CS=0x33,
NvBufferKind_V8Z24_MS8_VC8_2CS=0x34,
NvBufferKind_V8Z24_MS8_VC24_2CS=0x35,
NvBufferKind_V8Z24_MS4_VC12_2CZV=0x3a,
NvBufferKind_V8Z24_MS4_VC4_2CZV=0x3b,
NvBufferKind_V8Z24_MS8_VC8_2CZV=0x3C,
NvBufferKind_V8Z24_MS8_VC24_2CZV=0x3d,
NvBufferKind_V8Z24_MS4_VC12_2ZV=0x3e,
NvBufferKind_V8Z24_MS4_VC4_2ZV=0x3f,
NvBufferKind_V8Z24_MS8_VC8_2ZV=0x40,
NvBufferKind_V8Z24_MS8_VC24_2ZV=0x41,
NvBufferKind_V8Z24_MS4_VC12_4CSZV=0x42,
NvBufferKind_V8Z24_MS4_VC4_4CSZV=0x43,
NvBufferKind_V8Z24_MS8_VC8_4CSZV=0x44,
NvBufferKind_V8Z24_MS8_VC24_4CSZV=0x45,
NvBufferKind_Z24S8=0x46,
NvBufferKind_Z24S8_1Z=0x47,
NvBufferKind_Z24S8_MS2_1Z=0x48,
NvBufferKind_Z24S8_MS4_1Z=0x49,
NvBufferKind_Z24S8_MS8_1Z=0x4a,
NvBufferKind_Z24S8_MS16_1Z=0x4b,
NvBufferKind_Z24S8_2CS=0x4C,
NvBufferKind_Z24S8_MS2_2CS=0x4d,
NvBufferKind_Z24S8_MS4_2CS=0x4e,
NvBufferKind_Z24S8_MS8_2CS=0x4f,
NvBufferKind_Z24S8_MS16_2CS=0x50,
NvBufferKind_Z24S8_2CZ=0x51,
NvBufferKind_Z24S8_MS2_2CZ=0x52,
NvBufferKind_Z24S8_MS4_2CZ=0x53,
NvBufferKind_Z24S8_MS8_2CZ=0x54,
NvBufferKind_Z24S8_MS16_2CZ=0x55,
NvBufferKind_Z24S8_4CSZV=0x56,
NvBufferKind_Z24S8_MS2_4CSZV=0x57,
NvBufferKind_Z24S8_MS4_4CSZV=0x58,
NvBufferKind_Z24S8_MS8_4CSZV=0x59,
NvBufferKind_Z24S8_MS16_4CSZV=0x5a,
NvBufferKind_Z24V8_MS4_VC12=0x5b,
NvBufferKind_Z24V8_MS4_VC4=0x5C,
NvBufferKind_Z24V8_MS8_VC8=0x5d,
NvBufferKind_Z24V8_MS8_VC24=0x5e,
NvBufferKind_Z24V8_MS4_VC12_1ZV=0x63,
NvBufferKind_Z24V8_MS4_VC4_1ZV=0x64,
NvBufferKind_Z24V8_MS8_VC8_1ZV=0x65,
NvBufferKind_Z24V8_MS8_VC24_1ZV=0x66,
NvBufferKind_Z24V8_MS4_VC12_2CS=0x67,
NvBufferKind_Z24V8_MS4_VC4_2CS=0x68,
NvBufferKind_Z24V8_MS8_VC8_2CS=0x69,
NvBufferKind_Z24V8_MS8_VC24_2CS=0x6a,
NvBufferKind_Z24V8_MS4_VC12_2CZV=0x6f,
NvBufferKind_Z24V8_MS4_VC4_2CZV=0x70,
NvBufferKind_Z24V8_MS8_VC8_2CZV=0x71,
NvBufferKind_Z24V8_MS8_VC24_2CZV=0x72,
NvBufferKind_Z24V8_MS4_VC12_2ZV=0x73,
NvBufferKind_Z24V8_MS4_VC4_2ZV=0x74,
NvBufferKind_Z24V8_MS8_VC8_2ZV=0x75,
NvBufferKind_Z24V8_MS8_VC24_2ZV=0x76,
NvBufferKind_Z24V8_MS4_VC12_4CSZV=0x77,
NvBufferKind_Z24V8_MS4_VC4_4CSZV=0x78,
NvBufferKind_Z24V8_MS8_VC8_4CSZV=0x79,
NvBufferKind_Z24V8_MS8_VC24_4CSZV=0x7a,
NvBufferKind_ZF32=0x7b,
NvBufferKind_ZF32_1Z=0x7C,
NvBufferKind_ZF32_MS2_1Z=0x7d,
NvBufferKind_ZF32_MS4_1Z=0x7e,
NvBufferKind_ZF32_MS8_1Z=0x7f,
NvBufferKind_ZF32_MS16_1Z=0x80,
NvBufferKind_ZF32_2CS=0x81,
NvBufferKind_ZF32_MS2_2CS=0x82,
NvBufferKind_ZF32_MS4_2CS=0x83,
NvBufferKind_ZF32_MS8_2CS=0x84,
NvBufferKind_ZF32_MS16_2CS=0x85,
NvBufferKind_ZF32_2CZ=0x86,
NvBufferKind_ZF32_MS2_2CZ=0x87,
NvBufferKind_ZF32_MS4_2CZ=0x88,
NvBufferKind_ZF32_MS8_2CZ=0x89,
NvBufferKind_ZF32_MS16_2CZ=0x8a,
NvBufferKind_X8Z24_X16V8S8_MS4_VC12=0x8b,
NvBufferKind_X8Z24_X16V8S8_MS4_VC4=0x8C,
NvBufferKind_X8Z24_X16V8S8_MS8_VC8=0x8d,
NvBufferKind_X8Z24_X16V8S8_MS8_VC24=0x8e,
NvBufferKind_X8Z24_X16V8S8_MS4_VC12_1CS=0x8f,
NvBufferKind_X8Z24_X16V8S8_MS4_VC4_1CS=0x90,
NvBufferKind_X8Z24_X16V8S8_MS8_VC8_1CS=0x91,
NvBufferKind_X8Z24_X16V8S8_MS8_VC24_1CS=0x92,
NvBufferKind_X8Z24_X16V8S8_MS4_VC12_1ZV=0x97,
NvBufferKind_X8Z24_X16V8S8_MS4_VC4_1ZV=0x98,
NvBufferKind_X8Z24_X16V8S8_MS8_VC8_1ZV=0x99,
NvBufferKind_X8Z24_X16V8S8_MS8_VC24_1ZV=0x9a,
NvBufferKind_X8Z24_X16V8S8_MS4_VC12_1CZV=0x9b,
NvBufferKind_X8Z24_X16V8S8_MS4_VC4_1CZV=0x9C,
NvBufferKind_X8Z24_X16V8S8_MS8_VC8_1CZV=0x9d,
NvBufferKind_X8Z24_X16V8S8_MS8_VC24_1CZV=0x9e,
NvBufferKind_X8Z24_X16V8S8_MS4_VC12_2CS=0x9f,
NvBufferKind_X8Z24_X16V8S8_MS4_VC4_2CS=0xa0,
NvBufferKind_X8Z24_X16V8S8_MS8_VC8_2CS=0xa1,
NvBufferKind_X8Z24_X16V8S8_MS8_VC24_2CS=0xa2,
NvBufferKind_X8Z24_X16V8S8_MS4_VC12_2CSZV=0xa3,
NvBufferKind_X8Z24_X16V8S8_MS4_VC4_2CSZV=0xa4,
NvBufferKind_X8Z24_X16V8S8_MS8_VC8_2CSZV=0xa5,
NvBufferKind_X8Z24_X16V8S8_MS8_VC24_2CSZV=0xa6,
NvBufferKind_ZF32_X16V8S8_MS4_VC12=0xa7,
NvBufferKind_ZF32_X16V8S8_MS4_VC4=0xa8,
NvBufferKind_ZF32_X16V8S8_MS8_VC8=0xa9,
NvBufferKind_ZF32_X16V8S8_MS8_VC24=0xaa,
NvBufferKind_ZF32_X16V8S8_MS4_VC12_1CS=0xab,
NvBufferKind_ZF32_X16V8S8_MS4_VC4_1CS=0xaC,
NvBufferKind_ZF32_X16V8S8_MS8_VC8_1CS=0xad,
NvBufferKind_ZF32_X16V8S8_MS8_VC24_1CS=0xae,
NvBufferKind_ZF32_X16V8S8_MS4_VC12_1ZV=0xb3,
NvBufferKind_ZF32_X16V8S8_MS4_VC4_1ZV=0xb4,
NvBufferKind_ZF32_X16V8S8_MS8_VC8_1ZV=0xb5,
NvBufferKind_ZF32_X16V8S8_MS8_VC24_1ZV=0xb6,
NvBufferKind_ZF32_X16V8S8_MS4_VC12_1CZV=0xb7,
NvBufferKind_ZF32_X16V8S8_MS4_VC4_1CZV=0xb8,
NvBufferKind_ZF32_X16V8S8_MS8_VC8_1CZV=0xb9,
NvBufferKind_ZF32_X16V8S8_MS8_VC24_1CZV=0xba,
NvBufferKind_ZF32_X16V8S8_MS4_VC12_2CS=0xbb,
NvBufferKind_ZF32_X16V8S8_MS4_VC4_2CS=0xbC,
NvBufferKind_ZF32_X16V8S8_MS8_VC8_2CS=0xbd,
NvBufferKind_ZF32_X16V8S8_MS8_VC24_2CS=0xbe,
NvBufferKind_ZF32_X16V8S8_MS4_VC12_2CSZV=0xbf,
NvBufferKind_ZF32_X16V8S8_MS4_VC4_2CSZV=0xC0,
NvBufferKind_ZF32_X16V8S8_MS8_VC8_2CSZV=0xC1,
NvBufferKind_ZF32_X16V8S8_MS8_VC24_2CSZV=0xC2,
NvBufferKind_ZF32_X24S8=0xC3,
NvBufferKind_ZF32_X24S8_1CS=0xC4,
NvBufferKind_ZF32_X24S8_MS2_1CS=0xC5,
NvBufferKind_ZF32_X24S8_MS4_1CS=0xC6,
NvBufferKind_ZF32_X24S8_MS8_1CS=0xC7,
NvBufferKind_ZF32_X24S8_MS16_1CS=0xC8,
NvBufferKind_SmskedMessage=0xCa,
NvBufferKind_SmhostMessage=0xCb,
NvBufferKind_C64_MS2_2CRA=0xCd,
NvBufferKind_ZF32_X24S8_2CSZV=0xCe,
NvBufferKind_ZF32_X24S8_MS2_2CSZV=0xCf,
NvBufferKind_ZF32_X24S8_MS4_2CSZV=0xd0,
NvBufferKind_ZF32_X24S8_MS8_2CSZV=0xd1,
NvBufferKind_ZF32_X24S8_MS16_2CSZV=0xd2,
NvBufferKind_ZF32_X24S8_2CS=0xd3,
NvBufferKind_ZF32_X24S8_MS2_2CS=0xd4,
NvBufferKind_ZF32_X24S8_MS4_2CS=0xd5,
NvBufferKind_ZF32_X24S8_MS8_2CS=0xd6,
NvBufferKind_ZF32_X24S8_MS16_2CS=0xd7,
NvBufferKind_C32_2C=0xd8,
NvBufferKind_C32_2CBR=0xd9,
NvBufferKind_C32_2CBA=0xda,
NvBufferKind_C32_2CRA=0xdb,
NvBufferKind_C32_2BRA=0xdC,
NvBufferKind_C32_MS2_2C=0xdd,
NvBufferKind_C32_MS2_2CBR=0xde,
NvBufferKind_C32_MS2_2CRA=0xCC,
NvBufferKind_C32_MS4_2C=0xdf,
NvBufferKind_C32_MS4_2CBR=0xe0,
NvBufferKind_C32_MS4_2CBA=0xe1,
NvBufferKind_C32_MS4_2CRA=0xe2,
NvBufferKind_C32_MS4_2BRA=0xe3,
NvBufferKind_C32_MS8_MS16_2C=0xe4,
NvBufferKind_C32_MS8_MS16_2CRA=0xe5,
NvBufferKind_C64_2C=0xe6,
NvBufferKind_C64_2CBR=0xe7,
NvBufferKind_C64_2CBA=0xe8,
NvBufferKind_C64_2CRA=0xe9,
NvBufferKind_C64_2BRA=0xea,
NvBufferKind_C64_MS2_2C=0xeb,
NvBufferKind_C64_MS2_2CBR=0xeC,
NvBufferKind_C64_MS4_2C=0xed,
NvBufferKind_C64_MS4_2CBR=0xee,
NvBufferKind_C64_MS4_2CBA=0xef,
NvBufferKind_C64_MS4_2CRA=0xf0,
NvBufferKind_C64_MS4_2BRA=0xf1,
NvBufferKind_C64_MS8_MS16_2C=0xf2,
NvBufferKind_C64_MS8_MS16_2CRA=0xf3,
NvBufferKind_C128_2C=0xf4,
NvBufferKind_C128_2CR=0xf5,
NvBufferKind_C128_MS2_2C=0xf6,
NvBufferKind_C128_MS2_2CR=0xf7,
NvBufferKind_C128_MS4_2C=0xf8,
NvBufferKind_C128_MS4_2CR=0xf9,
NvBufferKind_C128_MS8_MS16_2C=0xfa,
NvBufferKind_C128_MS8_MS16_2CR=0xfb,
NvBufferKind_X8C24=0xfC,
NvBufferKind_PitchNoSwizzle=0xfd,
NvBufferKind_Generic_16BX2=0xfe,
NvBufferKind_Invalid=0xff,
} NvBufferKind;
Result nvbufInit();
Result nvbufExit();
Result nvbufCreate(NvBuffer* m, size_t size, u32 align, NvBufferKind kind);
Result nvbufCreateRw(NvBuffer* m, size_t size, u32 align, NvBufferKind kind);
void nvbufFree(NvBuffer* m);
void* nvbufGetAddr(NvBuffer* m);

256
nx/include/switch/nvidia/nvmap.h
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@ -1,256 +0,0 @@
#include "../types.h"
typedef struct {
u32 fd;
u32 size;
void* ptr;
} Nvmap;
typedef enum {
NvmapFlags_Writable=1
} NvmapFlags;
typedef enum {
NvmapKind_PitCh=0x0,
NvmapKind_Z16=0x1,
NvmapKind_Z16_2C=0x2,
NvmapKind_Z16_MS2_2C=0x3,
NvmapKind_Z16_MS4_2C=0x4,
NvmapKind_Z16_MS8_2C=0x5,
NvmapKind_Z16_MS16_2C=0x6,
NvmapKind_Z16_2Z=0x7,
NvmapKind_Z16_MS2_2Z=0x8,
NvmapKind_Z16_MS4_2Z=0x9,
NvmapKind_Z16_MS8_2Z=0xa,
NvmapKind_Z16_MS16_2Z=0xb,
NvmapKind_Z16_4CZ=0xC,
NvmapKind_Z16_MS2_4CZ=0xd,
NvmapKind_Z16_MS4_4CZ=0xe,
NvmapKind_Z16_MS8_4CZ=0xf,
NvmapKind_Z16_MS16_4CZ=0x10,
NvmapKind_S8Z24=0x11,
NvmapKind_S8Z24_1Z=0x12,
NvmapKind_S8Z24_MS2_1Z=0x13,
NvmapKind_S8Z24_MS4_1Z=0x14,
NvmapKind_S8Z24_MS8_1Z=0x15,
NvmapKind_S8Z24_MS16_1Z=0x16,
NvmapKind_S8Z24_2CZ=0x17,
NvmapKind_S8Z24_MS2_2CZ=0x18,
NvmapKind_S8Z24_MS4_2CZ=0x19,
NvmapKind_S8Z24_MS8_2CZ=0x1a,
NvmapKind_S8Z24_MS16_2CZ=0x1b,
NvmapKind_S8Z24_2CS=0x1C,
NvmapKind_S8Z24_MS2_2CS=0x1d,
NvmapKind_S8Z24_MS4_2CS=0x1e,
NvmapKind_S8Z24_MS8_2CS=0x1f,
NvmapKind_S8Z24_MS16_2CS=0x20,
NvmapKind_S8Z24_4CSZV=0x21,
NvmapKind_S8Z24_MS2_4CSZV=0x22,
NvmapKind_S8Z24_MS4_4CSZV=0x23,
NvmapKind_S8Z24_MS8_4CSZV=0x24,
NvmapKind_S8Z24_MS16_4CSZV=0x25,
NvmapKind_V8Z24_MS4_VC12=0x26,
NvmapKind_V8Z24_MS4_VC4=0x27,
NvmapKind_V8Z24_MS8_VC8=0x28,
NvmapKind_V8Z24_MS8_VC24=0x29,
NvmapKind_S8=0x2a,
NvmapKind_S8_2S=0x2b,
NvmapKind_V8Z24_MS4_VC12_1ZV=0x2e,
NvmapKind_V8Z24_MS4_VC4_1ZV=0x2f,
NvmapKind_V8Z24_MS8_VC8_1ZV=0x30,
NvmapKind_V8Z24_MS8_VC24_1ZV=0x31,
NvmapKind_V8Z24_MS4_VC12_2CS=0x32,
NvmapKind_V8Z24_MS4_VC4_2CS=0x33,
NvmapKind_V8Z24_MS8_VC8_2CS=0x34,
NvmapKind_V8Z24_MS8_VC24_2CS=0x35,
NvmapKind_V8Z24_MS4_VC12_2CZV=0x3a,
NvmapKind_V8Z24_MS4_VC4_2CZV=0x3b,
NvmapKind_V8Z24_MS8_VC8_2CZV=0x3C,
NvmapKind_V8Z24_MS8_VC24_2CZV=0x3d,
NvmapKind_V8Z24_MS4_VC12_2ZV=0x3e,
NvmapKind_V8Z24_MS4_VC4_2ZV=0x3f,
NvmapKind_V8Z24_MS8_VC8_2ZV=0x40,
NvmapKind_V8Z24_MS8_VC24_2ZV=0x41,
NvmapKind_V8Z24_MS4_VC12_4CSZV=0x42,
NvmapKind_V8Z24_MS4_VC4_4CSZV=0x43,
NvmapKind_V8Z24_MS8_VC8_4CSZV=0x44,
NvmapKind_V8Z24_MS8_VC24_4CSZV=0x45,
NvmapKind_Z24S8=0x46,
NvmapKind_Z24S8_1Z=0x47,
NvmapKind_Z24S8_MS2_1Z=0x48,
NvmapKind_Z24S8_MS4_1Z=0x49,
NvmapKind_Z24S8_MS8_1Z=0x4a,
NvmapKind_Z24S8_MS16_1Z=0x4b,
NvmapKind_Z24S8_2CS=0x4C,
NvmapKind_Z24S8_MS2_2CS=0x4d,
NvmapKind_Z24S8_MS4_2CS=0x4e,
NvmapKind_Z24S8_MS8_2CS=0x4f,
NvmapKind_Z24S8_MS16_2CS=0x50,
NvmapKind_Z24S8_2CZ=0x51,
NvmapKind_Z24S8_MS2_2CZ=0x52,
NvmapKind_Z24S8_MS4_2CZ=0x53,
NvmapKind_Z24S8_MS8_2CZ=0x54,
NvmapKind_Z24S8_MS16_2CZ=0x55,
NvmapKind_Z24S8_4CSZV=0x56,
NvmapKind_Z24S8_MS2_4CSZV=0x57,
NvmapKind_Z24S8_MS4_4CSZV=0x58,
NvmapKind_Z24S8_MS8_4CSZV=0x59,
NvmapKind_Z24S8_MS16_4CSZV=0x5a,
NvmapKind_Z24V8_MS4_VC12=0x5b,
NvmapKind_Z24V8_MS4_VC4=0x5C,
NvmapKind_Z24V8_MS8_VC8=0x5d,
NvmapKind_Z24V8_MS8_VC24=0x5e,
NvmapKind_Z24V8_MS4_VC12_1ZV=0x63,
NvmapKind_Z24V8_MS4_VC4_1ZV=0x64,
NvmapKind_Z24V8_MS8_VC8_1ZV=0x65,
NvmapKind_Z24V8_MS8_VC24_1ZV=0x66,
NvmapKind_Z24V8_MS4_VC12_2CS=0x67,
NvmapKind_Z24V8_MS4_VC4_2CS=0x68,
NvmapKind_Z24V8_MS8_VC8_2CS=0x69,
NvmapKind_Z24V8_MS8_VC24_2CS=0x6a,
NvmapKind_Z24V8_MS4_VC12_2CZV=0x6f,
NvmapKind_Z24V8_MS4_VC4_2CZV=0x70,
NvmapKind_Z24V8_MS8_VC8_2CZV=0x71,
NvmapKind_Z24V8_MS8_VC24_2CZV=0x72,
NvmapKind_Z24V8_MS4_VC12_2ZV=0x73,
NvmapKind_Z24V8_MS4_VC4_2ZV=0x74,
NvmapKind_Z24V8_MS8_VC8_2ZV=0x75,
NvmapKind_Z24V8_MS8_VC24_2ZV=0x76,
NvmapKind_Z24V8_MS4_VC12_4CSZV=0x77,
NvmapKind_Z24V8_MS4_VC4_4CSZV=0x78,
NvmapKind_Z24V8_MS8_VC8_4CSZV=0x79,
NvmapKind_Z24V8_MS8_VC24_4CSZV=0x7a,
NvmapKind_ZF32=0x7b,
NvmapKind_ZF32_1Z=0x7C,
NvmapKind_ZF32_MS2_1Z=0x7d,
NvmapKind_ZF32_MS4_1Z=0x7e,
NvmapKind_ZF32_MS8_1Z=0x7f,
NvmapKind_ZF32_MS16_1Z=0x80,
NvmapKind_ZF32_2CS=0x81,
NvmapKind_ZF32_MS2_2CS=0x82,
NvmapKind_ZF32_MS4_2CS=0x83,
NvmapKind_ZF32_MS8_2CS=0x84,
NvmapKind_ZF32_MS16_2CS=0x85,
NvmapKind_ZF32_2CZ=0x86,
NvmapKind_ZF32_MS2_2CZ=0x87,
NvmapKind_ZF32_MS4_2CZ=0x88,
NvmapKind_ZF32_MS8_2CZ=0x89,
NvmapKind_ZF32_MS16_2CZ=0x8a,
NvmapKind_X8Z24_X16V8S8_MS4_VC12=0x8b,
NvmapKind_X8Z24_X16V8S8_MS4_VC4=0x8C,
NvmapKind_X8Z24_X16V8S8_MS8_VC8=0x8d,
NvmapKind_X8Z24_X16V8S8_MS8_VC24=0x8e,
NvmapKind_X8Z24_X16V8S8_MS4_VC12_1CS=0x8f,
NvmapKind_X8Z24_X16V8S8_MS4_VC4_1CS=0x90,
NvmapKind_X8Z24_X16V8S8_MS8_VC8_1CS=0x91,
NvmapKind_X8Z24_X16V8S8_MS8_VC24_1CS=0x92,
NvmapKind_X8Z24_X16V8S8_MS4_VC12_1ZV=0x97,
NvmapKind_X8Z24_X16V8S8_MS4_VC4_1ZV=0x98,
NvmapKind_X8Z24_X16V8S8_MS8_VC8_1ZV=0x99,
NvmapKind_X8Z24_X16V8S8_MS8_VC24_1ZV=0x9a,
NvmapKind_X8Z24_X16V8S8_MS4_VC12_1CZV=0x9b,
NvmapKind_X8Z24_X16V8S8_MS4_VC4_1CZV=0x9C,
NvmapKind_X8Z24_X16V8S8_MS8_VC8_1CZV=0x9d,
NvmapKind_X8Z24_X16V8S8_MS8_VC24_1CZV=0x9e,
NvmapKind_X8Z24_X16V8S8_MS4_VC12_2CS=0x9f,
NvmapKind_X8Z24_X16V8S8_MS4_VC4_2CS=0xa0,
NvmapKind_X8Z24_X16V8S8_MS8_VC8_2CS=0xa1,
NvmapKind_X8Z24_X16V8S8_MS8_VC24_2CS=0xa2,
NvmapKind_X8Z24_X16V8S8_MS4_VC12_2CSZV=0xa3,
NvmapKind_X8Z24_X16V8S8_MS4_VC4_2CSZV=0xa4,
NvmapKind_X8Z24_X16V8S8_MS8_VC8_2CSZV=0xa5,
NvmapKind_X8Z24_X16V8S8_MS8_VC24_2CSZV=0xa6,
NvmapKind_ZF32_X16V8S8_MS4_VC12=0xa7,
NvmapKind_ZF32_X16V8S8_MS4_VC4=0xa8,
NvmapKind_ZF32_X16V8S8_MS8_VC8=0xa9,
NvmapKind_ZF32_X16V8S8_MS8_VC24=0xaa,
NvmapKind_ZF32_X16V8S8_MS4_VC12_1CS=0xab,
NvmapKind_ZF32_X16V8S8_MS4_VC4_1CS=0xaC,
NvmapKind_ZF32_X16V8S8_MS8_VC8_1CS=0xad,
NvmapKind_ZF32_X16V8S8_MS8_VC24_1CS=0xae,
NvmapKind_ZF32_X16V8S8_MS4_VC12_1ZV=0xb3,
NvmapKind_ZF32_X16V8S8_MS4_VC4_1ZV=0xb4,
NvmapKind_ZF32_X16V8S8_MS8_VC8_1ZV=0xb5,
NvmapKind_ZF32_X16V8S8_MS8_VC24_1ZV=0xb6,
NvmapKind_ZF32_X16V8S8_MS4_VC12_1CZV=0xb7,
NvmapKind_ZF32_X16V8S8_MS4_VC4_1CZV=0xb8,
NvmapKind_ZF32_X16V8S8_MS8_VC8_1CZV=0xb9,
NvmapKind_ZF32_X16V8S8_MS8_VC24_1CZV=0xba,
NvmapKind_ZF32_X16V8S8_MS4_VC12_2CS=0xbb,
NvmapKind_ZF32_X16V8S8_MS4_VC4_2CS=0xbC,
NvmapKind_ZF32_X16V8S8_MS8_VC8_2CS=0xbd,
NvmapKind_ZF32_X16V8S8_MS8_VC24_2CS=0xbe,
NvmapKind_ZF32_X16V8S8_MS4_VC12_2CSZV=0xbf,
NvmapKind_ZF32_X16V8S8_MS4_VC4_2CSZV=0xC0,
NvmapKind_ZF32_X16V8S8_MS8_VC8_2CSZV=0xC1,
NvmapKind_ZF32_X16V8S8_MS8_VC24_2CSZV=0xC2,
NvmapKind_ZF32_X24S8=0xC3,
NvmapKind_ZF32_X24S8_1CS=0xC4,
NvmapKind_ZF32_X24S8_MS2_1CS=0xC5,
NvmapKind_ZF32_X24S8_MS4_1CS=0xC6,
NvmapKind_ZF32_X24S8_MS8_1CS=0xC7,
NvmapKind_ZF32_X24S8_MS16_1CS=0xC8,
NvmapKind_SmskedMessage=0xCa,
NvmapKind_SmhostMessage=0xCb,
NvmapKind_C64_MS2_2CRA=0xCd,
NvmapKind_ZF32_X24S8_2CSZV=0xCe,
NvmapKind_ZF32_X24S8_MS2_2CSZV=0xCf,
NvmapKind_ZF32_X24S8_MS4_2CSZV=0xd0,
NvmapKind_ZF32_X24S8_MS8_2CSZV=0xd1,
NvmapKind_ZF32_X24S8_MS16_2CSZV=0xd2,
NvmapKind_ZF32_X24S8_2CS=0xd3,
NvmapKind_ZF32_X24S8_MS2_2CS=0xd4,
NvmapKind_ZF32_X24S8_MS4_2CS=0xd5,
NvmapKind_ZF32_X24S8_MS8_2CS=0xd6,
NvmapKind_ZF32_X24S8_MS16_2CS=0xd7,
NvmapKind_C32_2C=0xd8,
NvmapKind_C32_2CBR=0xd9,
NvmapKind_C32_2CBA=0xda,
NvmapKind_C32_2CRA=0xdb,
NvmapKind_C32_2BRA=0xdC,
NvmapKind_C32_MS2_2C=0xdd,
NvmapKind_C32_MS2_2CBR=0xde,
NvmapKind_C32_MS2_2CRA=0xCC,
NvmapKind_C32_MS4_2C=0xdf,
NvmapKind_C32_MS4_2CBR=0xe0,
NvmapKind_C32_MS4_2CBA=0xe1,
NvmapKind_C32_MS4_2CRA=0xe2,
NvmapKind_C32_MS4_2BRA=0xe3,
NvmapKind_C32_MS8_MS16_2C=0xe4,
NvmapKind_C32_MS8_MS16_2CRA=0xe5,
NvmapKind_C64_2C=0xe6,
NvmapKind_C64_2CBR=0xe7,
NvmapKind_C64_2CBA=0xe8,
NvmapKind_C64_2CRA=0xe9,
NvmapKind_C64_2BRA=0xea,
NvmapKind_C64_MS2_2C=0xeb,
NvmapKind_C64_MS2_2CBR=0xeC,
NvmapKind_C64_MS4_2C=0xed,
NvmapKind_C64_MS4_2CBR=0xee,
NvmapKind_C64_MS4_2CBA=0xef,
NvmapKind_C64_MS4_2CRA=0xf0,
NvmapKind_C64_MS4_2BRA=0xf1,
NvmapKind_C64_MS8_MS16_2C=0xf2,
NvmapKind_C64_MS8_MS16_2CRA=0xf3,
NvmapKind_C128_2C=0xf4,
NvmapKind_C128_2CR=0xf5,
NvmapKind_C128_MS2_2C=0xf6,
NvmapKind_C128_MS2_2CR=0xf7,
NvmapKind_C128_MS4_2C=0xf8,
NvmapKind_C128_MS4_2CR=0xf9,
NvmapKind_C128_MS8_MS16_2C=0xfa,
NvmapKind_C128_MS8_MS16_2CR=0xfb,
NvmapKind_X8C24=0xfC,
NvmapKind_PitchNoSwizzle=0xfd,
NvmapKind_Generic_16BX2=0xfe,
NvmapKind_Invalid=0xff,
} NvmapKind;
Result nvmapInit();
Result nvmapExit();
Result nvmapCreate(Nvmap* m, size_t size, u32 align, NvmapKind kind);
Result nvmapCreateRw(Nvmap* m, size_t size, u32 align, NvmapKind kind);
void nvmapFree(Nvmap* m);
void* nvmapGetAddr(Nvmap* m);

8
nx/source/nvidia/address_space.c
View File

@ -17,8 +17,12 @@ Result nvasCreate(NvAddressSpace* a)
Result nvasClose(NvAddressSpace* a) Result nvasClose(NvAddressSpace* a)
{ {
nvClose(a->fd); Result rc;
rc = nvClose(a->fd);
a->fd = -1; a->fd = -1;
return rc;
} }
Result nvasReserveAlign(NvAddressSpace* a, NvPageSize align, u32 pages, NvPageSize page_sz, iova_t* iova_out) { Result nvasReserveAlign(NvAddressSpace* a, NvPageSize align, u32 pages, NvPageSize page_sz, iova_t* iova_out) {
@ -33,6 +37,6 @@ Result nvasReserveFull(NvAddressSpace* a) {
return nvasReserveAlign(a, NvPageSize_64K, 0x10000, NvPageSize_64K, NULL); return nvasReserveAlign(a, NvPageSize_64K, 0x10000, NvPageSize_64K, NULL);
} }
Result nvasMapBuffer(NvAddressSpace* a, Nvmap* buffer, NvmapKind kind, iova_t* iova_out) { Result nvasMapBuffer(NvAddressSpace* a, NvBuffer* buffer, NvBufferKind kind, iova_t* iova_out) {
return nvioctlNvhostAsGpu_MapBufferEx(a->fd, 0, kind, buffer->fd, 0, 0, buffer->size, 0, iova_out); return nvioctlNvhostAsGpu_MapBufferEx(a->fd, 0, kind, buffer->fd, 0, 0, buffer->size, 0, iova_out);
} }

20
nx/source/nvidia/nvmap.c → nx/source/nvidia/buffer.c
View File

@ -3,19 +3,19 @@
#include "result.h" #include "result.h"
#include "services/nv.h" #include "services/nv.h"
#include "nvidia/ioctl.h" #include "nvidia/ioctl.h"
#include "nvidia/nvmap.h" #include "nvidia/buffer.h"
static u32 g_nvmap_fd; static u32 g_nvmap_fd;
Result nvmapInit() { Result nvbufInit() {
return nvOpen(&g_nvmap_fd, "/dev/nvmap"); return nvOpen(&g_nvmap_fd, "/dev/nvmap");
} }
Result nvmapExit() { Result nvbufExit() {
return nvClose(g_nvmap_fd); return nvClose(g_nvmap_fd);
} }
static Result _nvmapCreate(Nvmap* m, size_t size, u32 flags, u32 align, NvmapKind kind) static Result _nvbufCreate(NvBuffer* m, size_t size, u32 flags, u32 align, NvBufferKind kind)
{ {
Result rc; Result rc;
@ -45,15 +45,15 @@ static Result _nvmapCreate(Nvmap* m, size_t size, u32 flags, u32 align, NvmapKin
return rc; return rc;
} }
Result nvmapCreate(Nvmap* m, size_t size, u32 align, NvmapKind kind) { Result nvbufCreate(NvBuffer* m, size_t size, u32 align, NvBufferKind kind) {
return _nvmapCreate(m, size, 0, align, kind); return _nvbufCreate(m, size, 0, align, kind);
} }
Result nvmapCreateRw(Nvmap* m, size_t size, u32 align, NvmapKind kind) { Result nvbufCreateRw(NvBuffer* m, size_t size, u32 align, NvBufferKind kind) {
return _nvmapCreate(m, size, NvmapFlags_Writable, align, kind); return _nvbufCreate(m, size, NvBufferFlags_Writable, align, kind);
} }
void nvmapFree(Nvmap* m) void nvbufFree(NvBuffer* m)
{ {
free(m->ptr); free(m->ptr);
m->ptr = NULL; m->ptr = NULL;
@ -62,6 +62,6 @@ void nvmapFree(Nvmap* m)
m->fd = -1; m->fd = -1;
} }
void* nvmapGetAddr(Nvmap* m) { void* nvbufGetAddr(NvBuffer* m) {
return m->ptr; return m->ptr;
} }

3
nx/source/nvidia/ioctl/nvmap.c
View File

@ -2,8 +2,7 @@
#include "types.h" #include "types.h"
#include "result.h" #include "result.h"
#include "services/nv.h" #include "services/nv.h"
#include "display/ioctl.h" #include "nvidia/ioctl.h"
#include "display/nvioctl.h"
Result nvioctlNvmap_Create(u32 fd, u32 size, u32 *nvmap_handle) { Result nvioctlNvmap_Create(u32 fd, u32 size, u32 *nvmap_handle) {
Result rc=0; Result rc=0;