mirror of
https://github.com/switchbrew/libnx.git
synced 2025-06-21 12:32:40 +02:00
Rename nvmap->buffer
This commit is contained in:
plutooo
fincs
parent
04751087ca
commit
9a759c26f5
@ -72,7 +72,7 @@ extern "C" {
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#include "switch/display/nvgfx.h"
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#include "switch/nvidia/ioctl.h"
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#include "switch/nvidia/nvmap.h"
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#include "switch/nvidia/buffer.h"
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#include "switch/nvidia/address_space.h"
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#include "switch/audio/driver.h"
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@ -19,4 +19,4 @@ Result nvasReserveAlign(NvAddressSpace* a, NvPageSize align, u32 pages, NvPageSi
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Result nvasReserveAtFixedAddr(NvAddressSpace* a, iova_t addr, u32 pages, NvPageSize page_sz);
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Result nvasReserveFull(NvAddressSpace* a);
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Result nvasMapBuffer(NvAddressSpace* a, Nvmap* buffer, NvmapKind kind, iova_t* iova_out);
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Result nvasMapBuffer(NvAddressSpace* a, NvBuffer* buffer, NvBufferKind kind, iova_t* iova_out);
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258
nx/include/switch/nvidia/buffer.h
Normal file
258
nx/include/switch/nvidia/buffer.h
Normal file
@ -0,0 +1,258 @@
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#pragma once
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#include "../types.h"
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typedef struct {
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u32 fd;
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u32 size;
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void* ptr;
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} NvBuffer;
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typedef enum {
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NvBufferFlags_Writable=1
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} NvBufferFlags;
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typedef enum {
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NvBufferKind_PitCh=0x0,
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NvBufferKind_Z16=0x1,
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NvBufferKind_Z16_2C=0x2,
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NvBufferKind_Z16_MS2_2C=0x3,
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NvBufferKind_Z16_MS4_2C=0x4,
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NvBufferKind_Z16_MS8_2C=0x5,
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NvBufferKind_Z16_MS16_2C=0x6,
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NvBufferKind_Z16_2Z=0x7,
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NvBufferKind_Z16_MS2_2Z=0x8,
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NvBufferKind_Z16_MS4_2Z=0x9,
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NvBufferKind_Z16_MS8_2Z=0xa,
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NvBufferKind_Z16_MS16_2Z=0xb,
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NvBufferKind_Z16_4CZ=0xC,
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NvBufferKind_Z16_MS2_4CZ=0xd,
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NvBufferKind_Z16_MS4_4CZ=0xe,
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NvBufferKind_Z16_MS8_4CZ=0xf,
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NvBufferKind_Z16_MS16_4CZ=0x10,
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NvBufferKind_S8Z24=0x11,
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NvBufferKind_S8Z24_1Z=0x12,
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NvBufferKind_S8Z24_MS2_1Z=0x13,
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NvBufferKind_S8Z24_MS4_1Z=0x14,
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NvBufferKind_S8Z24_MS8_1Z=0x15,
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NvBufferKind_S8Z24_MS16_1Z=0x16,
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NvBufferKind_S8Z24_2CZ=0x17,
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NvBufferKind_S8Z24_MS2_2CZ=0x18,
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NvBufferKind_S8Z24_MS4_2CZ=0x19,
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NvBufferKind_S8Z24_MS8_2CZ=0x1a,
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NvBufferKind_S8Z24_MS16_2CZ=0x1b,
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NvBufferKind_S8Z24_2CS=0x1C,
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NvBufferKind_S8Z24_MS2_2CS=0x1d,
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NvBufferKind_S8Z24_MS4_2CS=0x1e,
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NvBufferKind_S8Z24_MS8_2CS=0x1f,
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NvBufferKind_S8Z24_MS16_2CS=0x20,
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NvBufferKind_S8Z24_4CSZV=0x21,
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NvBufferKind_S8Z24_MS2_4CSZV=0x22,
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NvBufferKind_S8Z24_MS4_4CSZV=0x23,
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NvBufferKind_S8Z24_MS8_4CSZV=0x24,
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NvBufferKind_S8Z24_MS16_4CSZV=0x25,
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NvBufferKind_V8Z24_MS4_VC12=0x26,
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NvBufferKind_V8Z24_MS4_VC4=0x27,
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NvBufferKind_V8Z24_MS8_VC8=0x28,
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NvBufferKind_V8Z24_MS8_VC24=0x29,
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NvBufferKind_S8=0x2a,
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NvBufferKind_S8_2S=0x2b,
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NvBufferKind_V8Z24_MS4_VC12_1ZV=0x2e,
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NvBufferKind_V8Z24_MS4_VC4_1ZV=0x2f,
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NvBufferKind_V8Z24_MS8_VC8_1ZV=0x30,
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NvBufferKind_V8Z24_MS8_VC24_1ZV=0x31,
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NvBufferKind_V8Z24_MS4_VC12_2CS=0x32,
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NvBufferKind_V8Z24_MS4_VC4_2CS=0x33,
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NvBufferKind_V8Z24_MS8_VC8_2CS=0x34,
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NvBufferKind_V8Z24_MS8_VC24_2CS=0x35,
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NvBufferKind_V8Z24_MS4_VC12_2CZV=0x3a,
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NvBufferKind_V8Z24_MS4_VC4_2CZV=0x3b,
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NvBufferKind_V8Z24_MS8_VC8_2CZV=0x3C,
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NvBufferKind_V8Z24_MS8_VC24_2CZV=0x3d,
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NvBufferKind_V8Z24_MS4_VC12_2ZV=0x3e,
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NvBufferKind_V8Z24_MS4_VC4_2ZV=0x3f,
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NvBufferKind_V8Z24_MS8_VC8_2ZV=0x40,
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NvBufferKind_V8Z24_MS8_VC24_2ZV=0x41,
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NvBufferKind_V8Z24_MS4_VC12_4CSZV=0x42,
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NvBufferKind_V8Z24_MS4_VC4_4CSZV=0x43,
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NvBufferKind_V8Z24_MS8_VC8_4CSZV=0x44,
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NvBufferKind_V8Z24_MS8_VC24_4CSZV=0x45,
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NvBufferKind_Z24S8=0x46,
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NvBufferKind_Z24S8_1Z=0x47,
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NvBufferKind_Z24S8_MS2_1Z=0x48,
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NvBufferKind_Z24S8_MS4_1Z=0x49,
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NvBufferKind_Z24S8_MS8_1Z=0x4a,
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NvBufferKind_Z24S8_MS16_1Z=0x4b,
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NvBufferKind_Z24S8_2CS=0x4C,
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NvBufferKind_Z24S8_MS2_2CS=0x4d,
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NvBufferKind_Z24S8_MS4_2CS=0x4e,
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NvBufferKind_Z24S8_MS8_2CS=0x4f,
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NvBufferKind_Z24S8_MS16_2CS=0x50,
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NvBufferKind_Z24S8_2CZ=0x51,
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NvBufferKind_Z24S8_MS2_2CZ=0x52,
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NvBufferKind_Z24S8_MS4_2CZ=0x53,
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NvBufferKind_Z24S8_MS8_2CZ=0x54,
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NvBufferKind_Z24S8_MS16_2CZ=0x55,
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NvBufferKind_Z24S8_4CSZV=0x56,
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NvBufferKind_Z24S8_MS2_4CSZV=0x57,
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NvBufferKind_Z24S8_MS4_4CSZV=0x58,
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NvBufferKind_Z24S8_MS8_4CSZV=0x59,
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NvBufferKind_Z24S8_MS16_4CSZV=0x5a,
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NvBufferKind_Z24V8_MS4_VC12=0x5b,
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NvBufferKind_Z24V8_MS4_VC4=0x5C,
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NvBufferKind_Z24V8_MS8_VC8=0x5d,
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NvBufferKind_Z24V8_MS8_VC24=0x5e,
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NvBufferKind_Z24V8_MS4_VC12_1ZV=0x63,
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NvBufferKind_Z24V8_MS4_VC4_1ZV=0x64,
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NvBufferKind_Z24V8_MS8_VC8_1ZV=0x65,
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NvBufferKind_Z24V8_MS8_VC24_1ZV=0x66,
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NvBufferKind_Z24V8_MS4_VC12_2CS=0x67,
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NvBufferKind_Z24V8_MS4_VC4_2CS=0x68,
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NvBufferKind_Z24V8_MS8_VC8_2CS=0x69,
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NvBufferKind_Z24V8_MS8_VC24_2CS=0x6a,
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NvBufferKind_Z24V8_MS4_VC12_2CZV=0x6f,
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NvBufferKind_Z24V8_MS4_VC4_2CZV=0x70,
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NvBufferKind_Z24V8_MS8_VC8_2CZV=0x71,
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NvBufferKind_Z24V8_MS8_VC24_2CZV=0x72,
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NvBufferKind_Z24V8_MS4_VC12_2ZV=0x73,
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NvBufferKind_Z24V8_MS4_VC4_2ZV=0x74,
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NvBufferKind_Z24V8_MS8_VC8_2ZV=0x75,
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NvBufferKind_Z24V8_MS8_VC24_2ZV=0x76,
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NvBufferKind_Z24V8_MS4_VC12_4CSZV=0x77,
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NvBufferKind_Z24V8_MS4_VC4_4CSZV=0x78,
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NvBufferKind_Z24V8_MS8_VC8_4CSZV=0x79,
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NvBufferKind_Z24V8_MS8_VC24_4CSZV=0x7a,
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NvBufferKind_ZF32=0x7b,
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NvBufferKind_ZF32_1Z=0x7C,
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NvBufferKind_ZF32_MS2_1Z=0x7d,
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NvBufferKind_ZF32_MS4_1Z=0x7e,
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NvBufferKind_ZF32_MS8_1Z=0x7f,
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NvBufferKind_ZF32_MS16_1Z=0x80,
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NvBufferKind_ZF32_2CS=0x81,
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NvBufferKind_ZF32_MS2_2CS=0x82,
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NvBufferKind_ZF32_MS4_2CS=0x83,
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NvBufferKind_ZF32_MS8_2CS=0x84,
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NvBufferKind_ZF32_MS16_2CS=0x85,
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NvBufferKind_ZF32_2CZ=0x86,
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NvBufferKind_ZF32_MS2_2CZ=0x87,
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NvBufferKind_ZF32_MS4_2CZ=0x88,
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NvBufferKind_ZF32_MS8_2CZ=0x89,
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NvBufferKind_ZF32_MS16_2CZ=0x8a,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC12=0x8b,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC4=0x8C,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC8=0x8d,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC24=0x8e,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC12_1CS=0x8f,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC4_1CS=0x90,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC8_1CS=0x91,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC24_1CS=0x92,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC12_1ZV=0x97,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC4_1ZV=0x98,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC8_1ZV=0x99,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC24_1ZV=0x9a,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC12_1CZV=0x9b,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC4_1CZV=0x9C,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC8_1CZV=0x9d,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC24_1CZV=0x9e,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC12_2CS=0x9f,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC4_2CS=0xa0,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC8_2CS=0xa1,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC24_2CS=0xa2,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC12_2CSZV=0xa3,
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NvBufferKind_X8Z24_X16V8S8_MS4_VC4_2CSZV=0xa4,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC8_2CSZV=0xa5,
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NvBufferKind_X8Z24_X16V8S8_MS8_VC24_2CSZV=0xa6,
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NvBufferKind_ZF32_X16V8S8_MS4_VC12=0xa7,
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NvBufferKind_ZF32_X16V8S8_MS4_VC4=0xa8,
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NvBufferKind_ZF32_X16V8S8_MS8_VC8=0xa9,
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NvBufferKind_ZF32_X16V8S8_MS8_VC24=0xaa,
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NvBufferKind_ZF32_X16V8S8_MS4_VC12_1CS=0xab,
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NvBufferKind_ZF32_X16V8S8_MS4_VC4_1CS=0xaC,
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NvBufferKind_ZF32_X16V8S8_MS8_VC8_1CS=0xad,
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NvBufferKind_ZF32_X16V8S8_MS8_VC24_1CS=0xae,
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NvBufferKind_ZF32_X16V8S8_MS4_VC12_1ZV=0xb3,
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NvBufferKind_ZF32_X16V8S8_MS4_VC4_1ZV=0xb4,
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NvBufferKind_ZF32_X16V8S8_MS8_VC8_1ZV=0xb5,
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NvBufferKind_ZF32_X16V8S8_MS8_VC24_1ZV=0xb6,
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NvBufferKind_ZF32_X16V8S8_MS4_VC12_1CZV=0xb7,
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NvBufferKind_ZF32_X16V8S8_MS4_VC4_1CZV=0xb8,
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NvBufferKind_ZF32_X16V8S8_MS8_VC8_1CZV=0xb9,
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NvBufferKind_ZF32_X16V8S8_MS8_VC24_1CZV=0xba,
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NvBufferKind_ZF32_X16V8S8_MS4_VC12_2CS=0xbb,
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NvBufferKind_ZF32_X16V8S8_MS4_VC4_2CS=0xbC,
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NvBufferKind_ZF32_X16V8S8_MS8_VC8_2CS=0xbd,
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NvBufferKind_ZF32_X16V8S8_MS8_VC24_2CS=0xbe,
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NvBufferKind_ZF32_X16V8S8_MS4_VC12_2CSZV=0xbf,
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NvBufferKind_ZF32_X16V8S8_MS4_VC4_2CSZV=0xC0,
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NvBufferKind_ZF32_X16V8S8_MS8_VC8_2CSZV=0xC1,
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NvBufferKind_ZF32_X16V8S8_MS8_VC24_2CSZV=0xC2,
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NvBufferKind_ZF32_X24S8=0xC3,
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NvBufferKind_ZF32_X24S8_1CS=0xC4,
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NvBufferKind_ZF32_X24S8_MS2_1CS=0xC5,
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NvBufferKind_ZF32_X24S8_MS4_1CS=0xC6,
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NvBufferKind_ZF32_X24S8_MS8_1CS=0xC7,
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NvBufferKind_ZF32_X24S8_MS16_1CS=0xC8,
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NvBufferKind_SmskedMessage=0xCa,
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NvBufferKind_SmhostMessage=0xCb,
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NvBufferKind_C64_MS2_2CRA=0xCd,
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NvBufferKind_ZF32_X24S8_2CSZV=0xCe,
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NvBufferKind_ZF32_X24S8_MS2_2CSZV=0xCf,
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NvBufferKind_ZF32_X24S8_MS4_2CSZV=0xd0,
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NvBufferKind_ZF32_X24S8_MS8_2CSZV=0xd1,
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NvBufferKind_ZF32_X24S8_MS16_2CSZV=0xd2,
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NvBufferKind_ZF32_X24S8_2CS=0xd3,
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NvBufferKind_ZF32_X24S8_MS2_2CS=0xd4,
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NvBufferKind_ZF32_X24S8_MS4_2CS=0xd5,
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NvBufferKind_ZF32_X24S8_MS8_2CS=0xd6,
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NvBufferKind_ZF32_X24S8_MS16_2CS=0xd7,
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NvBufferKind_C32_2C=0xd8,
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NvBufferKind_C32_2CBR=0xd9,
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NvBufferKind_C32_2CBA=0xda,
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NvBufferKind_C32_2CRA=0xdb,
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NvBufferKind_C32_2BRA=0xdC,
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NvBufferKind_C32_MS2_2C=0xdd,
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NvBufferKind_C32_MS2_2CBR=0xde,
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NvBufferKind_C32_MS2_2CRA=0xCC,
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NvBufferKind_C32_MS4_2C=0xdf,
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NvBufferKind_C32_MS4_2CBR=0xe0,
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NvBufferKind_C32_MS4_2CBA=0xe1,
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NvBufferKind_C32_MS4_2CRA=0xe2,
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NvBufferKind_C32_MS4_2BRA=0xe3,
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NvBufferKind_C32_MS8_MS16_2C=0xe4,
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NvBufferKind_C32_MS8_MS16_2CRA=0xe5,
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NvBufferKind_C64_2C=0xe6,
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NvBufferKind_C64_2CBR=0xe7,
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NvBufferKind_C64_2CBA=0xe8,
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NvBufferKind_C64_2CRA=0xe9,
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NvBufferKind_C64_2BRA=0xea,
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NvBufferKind_C64_MS2_2C=0xeb,
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NvBufferKind_C64_MS2_2CBR=0xeC,
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NvBufferKind_C64_MS4_2C=0xed,
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NvBufferKind_C64_MS4_2CBR=0xee,
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NvBufferKind_C64_MS4_2CBA=0xef,
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NvBufferKind_C64_MS4_2CRA=0xf0,
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NvBufferKind_C64_MS4_2BRA=0xf1,
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NvBufferKind_C64_MS8_MS16_2C=0xf2,
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NvBufferKind_C64_MS8_MS16_2CRA=0xf3,
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NvBufferKind_C128_2C=0xf4,
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NvBufferKind_C128_2CR=0xf5,
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NvBufferKind_C128_MS2_2C=0xf6,
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NvBufferKind_C128_MS2_2CR=0xf7,
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NvBufferKind_C128_MS4_2C=0xf8,
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NvBufferKind_C128_MS4_2CR=0xf9,
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NvBufferKind_C128_MS8_MS16_2C=0xfa,
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NvBufferKind_C128_MS8_MS16_2CR=0xfb,
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NvBufferKind_X8C24=0xfC,
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NvBufferKind_PitchNoSwizzle=0xfd,
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NvBufferKind_Generic_16BX2=0xfe,
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NvBufferKind_Invalid=0xff,
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} NvBufferKind;
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Result nvbufInit();
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Result nvbufExit();
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Result nvbufCreate(NvBuffer* m, size_t size, u32 align, NvBufferKind kind);
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Result nvbufCreateRw(NvBuffer* m, size_t size, u32 align, NvBufferKind kind);
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void nvbufFree(NvBuffer* m);
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void* nvbufGetAddr(NvBuffer* m);
|
||||
@ -1,256 +0,0 @@
|
||||
#include "../types.h"
|
||||
|
||||
typedef struct {
|
||||
u32 fd;
|
||||
u32 size;
|
||||
void* ptr;
|
||||
} Nvmap;
|
||||
|
||||
typedef enum {
|
||||
NvmapFlags_Writable=1
|
||||
} NvmapFlags;
|
||||
|
||||
typedef enum {
|
||||
NvmapKind_PitCh=0x0,
|
||||
NvmapKind_Z16=0x1,
|
||||
NvmapKind_Z16_2C=0x2,
|
||||
NvmapKind_Z16_MS2_2C=0x3,
|
||||
NvmapKind_Z16_MS4_2C=0x4,
|
||||
NvmapKind_Z16_MS8_2C=0x5,
|
||||
NvmapKind_Z16_MS16_2C=0x6,
|
||||
NvmapKind_Z16_2Z=0x7,
|
||||
NvmapKind_Z16_MS2_2Z=0x8,
|
||||
NvmapKind_Z16_MS4_2Z=0x9,
|
||||
NvmapKind_Z16_MS8_2Z=0xa,
|
||||
NvmapKind_Z16_MS16_2Z=0xb,
|
||||
NvmapKind_Z16_4CZ=0xC,
|
||||
NvmapKind_Z16_MS2_4CZ=0xd,
|
||||
NvmapKind_Z16_MS4_4CZ=0xe,
|
||||
NvmapKind_Z16_MS8_4CZ=0xf,
|
||||
NvmapKind_Z16_MS16_4CZ=0x10,
|
||||
NvmapKind_S8Z24=0x11,
|
||||
NvmapKind_S8Z24_1Z=0x12,
|
||||
NvmapKind_S8Z24_MS2_1Z=0x13,
|
||||
NvmapKind_S8Z24_MS4_1Z=0x14,
|
||||
NvmapKind_S8Z24_MS8_1Z=0x15,
|
||||
NvmapKind_S8Z24_MS16_1Z=0x16,
|
||||
NvmapKind_S8Z24_2CZ=0x17,
|
||||
NvmapKind_S8Z24_MS2_2CZ=0x18,
|
||||
NvmapKind_S8Z24_MS4_2CZ=0x19,
|
||||
NvmapKind_S8Z24_MS8_2CZ=0x1a,
|
||||
NvmapKind_S8Z24_MS16_2CZ=0x1b,
|
||||
NvmapKind_S8Z24_2CS=0x1C,
|
||||
NvmapKind_S8Z24_MS2_2CS=0x1d,
|
||||
NvmapKind_S8Z24_MS4_2CS=0x1e,
|
||||
NvmapKind_S8Z24_MS8_2CS=0x1f,
|
||||
NvmapKind_S8Z24_MS16_2CS=0x20,
|
||||
NvmapKind_S8Z24_4CSZV=0x21,
|
||||
NvmapKind_S8Z24_MS2_4CSZV=0x22,
|
||||
NvmapKind_S8Z24_MS4_4CSZV=0x23,
|
||||
NvmapKind_S8Z24_MS8_4CSZV=0x24,
|
||||
NvmapKind_S8Z24_MS16_4CSZV=0x25,
|
||||
NvmapKind_V8Z24_MS4_VC12=0x26,
|
||||
NvmapKind_V8Z24_MS4_VC4=0x27,
|
||||
NvmapKind_V8Z24_MS8_VC8=0x28,
|
||||
NvmapKind_V8Z24_MS8_VC24=0x29,
|
||||
NvmapKind_S8=0x2a,
|
||||
NvmapKind_S8_2S=0x2b,
|
||||
NvmapKind_V8Z24_MS4_VC12_1ZV=0x2e,
|
||||
NvmapKind_V8Z24_MS4_VC4_1ZV=0x2f,
|
||||
NvmapKind_V8Z24_MS8_VC8_1ZV=0x30,
|
||||
NvmapKind_V8Z24_MS8_VC24_1ZV=0x31,
|
||||
NvmapKind_V8Z24_MS4_VC12_2CS=0x32,
|
||||
NvmapKind_V8Z24_MS4_VC4_2CS=0x33,
|
||||
NvmapKind_V8Z24_MS8_VC8_2CS=0x34,
|
||||
NvmapKind_V8Z24_MS8_VC24_2CS=0x35,
|
||||
NvmapKind_V8Z24_MS4_VC12_2CZV=0x3a,
|
||||
NvmapKind_V8Z24_MS4_VC4_2CZV=0x3b,
|
||||
NvmapKind_V8Z24_MS8_VC8_2CZV=0x3C,
|
||||
NvmapKind_V8Z24_MS8_VC24_2CZV=0x3d,
|
||||
NvmapKind_V8Z24_MS4_VC12_2ZV=0x3e,
|
||||
NvmapKind_V8Z24_MS4_VC4_2ZV=0x3f,
|
||||
NvmapKind_V8Z24_MS8_VC8_2ZV=0x40,
|
||||
NvmapKind_V8Z24_MS8_VC24_2ZV=0x41,
|
||||
NvmapKind_V8Z24_MS4_VC12_4CSZV=0x42,
|
||||
NvmapKind_V8Z24_MS4_VC4_4CSZV=0x43,
|
||||
NvmapKind_V8Z24_MS8_VC8_4CSZV=0x44,
|
||||
NvmapKind_V8Z24_MS8_VC24_4CSZV=0x45,
|
||||
NvmapKind_Z24S8=0x46,
|
||||
NvmapKind_Z24S8_1Z=0x47,
|
||||
NvmapKind_Z24S8_MS2_1Z=0x48,
|
||||
NvmapKind_Z24S8_MS4_1Z=0x49,
|
||||
NvmapKind_Z24S8_MS8_1Z=0x4a,
|
||||
NvmapKind_Z24S8_MS16_1Z=0x4b,
|
||||
NvmapKind_Z24S8_2CS=0x4C,
|
||||
NvmapKind_Z24S8_MS2_2CS=0x4d,
|
||||
NvmapKind_Z24S8_MS4_2CS=0x4e,
|
||||
NvmapKind_Z24S8_MS8_2CS=0x4f,
|
||||
NvmapKind_Z24S8_MS16_2CS=0x50,
|
||||
NvmapKind_Z24S8_2CZ=0x51,
|
||||
NvmapKind_Z24S8_MS2_2CZ=0x52,
|
||||
NvmapKind_Z24S8_MS4_2CZ=0x53,
|
||||
NvmapKind_Z24S8_MS8_2CZ=0x54,
|
||||
NvmapKind_Z24S8_MS16_2CZ=0x55,
|
||||
NvmapKind_Z24S8_4CSZV=0x56,
|
||||
NvmapKind_Z24S8_MS2_4CSZV=0x57,
|
||||
NvmapKind_Z24S8_MS4_4CSZV=0x58,
|
||||
NvmapKind_Z24S8_MS8_4CSZV=0x59,
|
||||
NvmapKind_Z24S8_MS16_4CSZV=0x5a,
|
||||
NvmapKind_Z24V8_MS4_VC12=0x5b,
|
||||
NvmapKind_Z24V8_MS4_VC4=0x5C,
|
||||
NvmapKind_Z24V8_MS8_VC8=0x5d,
|
||||
NvmapKind_Z24V8_MS8_VC24=0x5e,
|
||||
NvmapKind_Z24V8_MS4_VC12_1ZV=0x63,
|
||||
NvmapKind_Z24V8_MS4_VC4_1ZV=0x64,
|
||||
NvmapKind_Z24V8_MS8_VC8_1ZV=0x65,
|
||||
NvmapKind_Z24V8_MS8_VC24_1ZV=0x66,
|
||||
NvmapKind_Z24V8_MS4_VC12_2CS=0x67,
|
||||
NvmapKind_Z24V8_MS4_VC4_2CS=0x68,
|
||||
NvmapKind_Z24V8_MS8_VC8_2CS=0x69,
|
||||
NvmapKind_Z24V8_MS8_VC24_2CS=0x6a,
|
||||
NvmapKind_Z24V8_MS4_VC12_2CZV=0x6f,
|
||||
NvmapKind_Z24V8_MS4_VC4_2CZV=0x70,
|
||||
NvmapKind_Z24V8_MS8_VC8_2CZV=0x71,
|
||||
NvmapKind_Z24V8_MS8_VC24_2CZV=0x72,
|
||||
NvmapKind_Z24V8_MS4_VC12_2ZV=0x73,
|
||||
NvmapKind_Z24V8_MS4_VC4_2ZV=0x74,
|
||||
NvmapKind_Z24V8_MS8_VC8_2ZV=0x75,
|
||||
NvmapKind_Z24V8_MS8_VC24_2ZV=0x76,
|
||||
NvmapKind_Z24V8_MS4_VC12_4CSZV=0x77,
|
||||
NvmapKind_Z24V8_MS4_VC4_4CSZV=0x78,
|
||||
NvmapKind_Z24V8_MS8_VC8_4CSZV=0x79,
|
||||
NvmapKind_Z24V8_MS8_VC24_4CSZV=0x7a,
|
||||
NvmapKind_ZF32=0x7b,
|
||||
NvmapKind_ZF32_1Z=0x7C,
|
||||
NvmapKind_ZF32_MS2_1Z=0x7d,
|
||||
NvmapKind_ZF32_MS4_1Z=0x7e,
|
||||
NvmapKind_ZF32_MS8_1Z=0x7f,
|
||||
NvmapKind_ZF32_MS16_1Z=0x80,
|
||||
NvmapKind_ZF32_2CS=0x81,
|
||||
NvmapKind_ZF32_MS2_2CS=0x82,
|
||||
NvmapKind_ZF32_MS4_2CS=0x83,
|
||||
NvmapKind_ZF32_MS8_2CS=0x84,
|
||||
NvmapKind_ZF32_MS16_2CS=0x85,
|
||||
NvmapKind_ZF32_2CZ=0x86,
|
||||
NvmapKind_ZF32_MS2_2CZ=0x87,
|
||||
NvmapKind_ZF32_MS4_2CZ=0x88,
|
||||
NvmapKind_ZF32_MS8_2CZ=0x89,
|
||||
NvmapKind_ZF32_MS16_2CZ=0x8a,
|
||||
NvmapKind_X8Z24_X16V8S8_MS4_VC12=0x8b,
|
||||
NvmapKind_X8Z24_X16V8S8_MS4_VC4=0x8C,
|
||||
NvmapKind_X8Z24_X16V8S8_MS8_VC8=0x8d,
|
||||
NvmapKind_X8Z24_X16V8S8_MS8_VC24=0x8e,
|
||||
NvmapKind_X8Z24_X16V8S8_MS4_VC12_1CS=0x8f,
|
||||
NvmapKind_X8Z24_X16V8S8_MS4_VC4_1CS=0x90,
|
||||
NvmapKind_X8Z24_X16V8S8_MS8_VC8_1CS=0x91,
|
||||
NvmapKind_X8Z24_X16V8S8_MS8_VC24_1CS=0x92,
|
||||
NvmapKind_X8Z24_X16V8S8_MS4_VC12_1ZV=0x97,
|
||||
NvmapKind_X8Z24_X16V8S8_MS4_VC4_1ZV=0x98,
|
||||
NvmapKind_X8Z24_X16V8S8_MS8_VC8_1ZV=0x99,
|
||||
NvmapKind_X8Z24_X16V8S8_MS8_VC24_1ZV=0x9a,
|
||||
NvmapKind_X8Z24_X16V8S8_MS4_VC12_1CZV=0x9b,
|
||||
NvmapKind_X8Z24_X16V8S8_MS4_VC4_1CZV=0x9C,
|
||||
NvmapKind_X8Z24_X16V8S8_MS8_VC8_1CZV=0x9d,
|
||||
NvmapKind_X8Z24_X16V8S8_MS8_VC24_1CZV=0x9e,
|
||||
NvmapKind_X8Z24_X16V8S8_MS4_VC12_2CS=0x9f,
|
||||
NvmapKind_X8Z24_X16V8S8_MS4_VC4_2CS=0xa0,
|
||||
NvmapKind_X8Z24_X16V8S8_MS8_VC8_2CS=0xa1,
|
||||
NvmapKind_X8Z24_X16V8S8_MS8_VC24_2CS=0xa2,
|
||||
NvmapKind_X8Z24_X16V8S8_MS4_VC12_2CSZV=0xa3,
|
||||
NvmapKind_X8Z24_X16V8S8_MS4_VC4_2CSZV=0xa4,
|
||||
NvmapKind_X8Z24_X16V8S8_MS8_VC8_2CSZV=0xa5,
|
||||
NvmapKind_X8Z24_X16V8S8_MS8_VC24_2CSZV=0xa6,
|
||||
NvmapKind_ZF32_X16V8S8_MS4_VC12=0xa7,
|
||||
NvmapKind_ZF32_X16V8S8_MS4_VC4=0xa8,
|
||||
NvmapKind_ZF32_X16V8S8_MS8_VC8=0xa9,
|
||||
NvmapKind_ZF32_X16V8S8_MS8_VC24=0xaa,
|
||||
NvmapKind_ZF32_X16V8S8_MS4_VC12_1CS=0xab,
|
||||
NvmapKind_ZF32_X16V8S8_MS4_VC4_1CS=0xaC,
|
||||
NvmapKind_ZF32_X16V8S8_MS8_VC8_1CS=0xad,
|
||||
NvmapKind_ZF32_X16V8S8_MS8_VC24_1CS=0xae,
|
||||
NvmapKind_ZF32_X16V8S8_MS4_VC12_1ZV=0xb3,
|
||||
NvmapKind_ZF32_X16V8S8_MS4_VC4_1ZV=0xb4,
|
||||
NvmapKind_ZF32_X16V8S8_MS8_VC8_1ZV=0xb5,
|
||||
NvmapKind_ZF32_X16V8S8_MS8_VC24_1ZV=0xb6,
|
||||
NvmapKind_ZF32_X16V8S8_MS4_VC12_1CZV=0xb7,
|
||||
NvmapKind_ZF32_X16V8S8_MS4_VC4_1CZV=0xb8,
|
||||
NvmapKind_ZF32_X16V8S8_MS8_VC8_1CZV=0xb9,
|
||||
NvmapKind_ZF32_X16V8S8_MS8_VC24_1CZV=0xba,
|
||||
NvmapKind_ZF32_X16V8S8_MS4_VC12_2CS=0xbb,
|
||||
NvmapKind_ZF32_X16V8S8_MS4_VC4_2CS=0xbC,
|
||||
NvmapKind_ZF32_X16V8S8_MS8_VC8_2CS=0xbd,
|
||||
NvmapKind_ZF32_X16V8S8_MS8_VC24_2CS=0xbe,
|
||||
NvmapKind_ZF32_X16V8S8_MS4_VC12_2CSZV=0xbf,
|
||||
NvmapKind_ZF32_X16V8S8_MS4_VC4_2CSZV=0xC0,
|
||||
NvmapKind_ZF32_X16V8S8_MS8_VC8_2CSZV=0xC1,
|
||||
NvmapKind_ZF32_X16V8S8_MS8_VC24_2CSZV=0xC2,
|
||||
NvmapKind_ZF32_X24S8=0xC3,
|
||||
NvmapKind_ZF32_X24S8_1CS=0xC4,
|
||||
NvmapKind_ZF32_X24S8_MS2_1CS=0xC5,
|
||||
NvmapKind_ZF32_X24S8_MS4_1CS=0xC6,
|
||||
NvmapKind_ZF32_X24S8_MS8_1CS=0xC7,
|
||||
NvmapKind_ZF32_X24S8_MS16_1CS=0xC8,
|
||||
NvmapKind_SmskedMessage=0xCa,
|
||||
NvmapKind_SmhostMessage=0xCb,
|
||||
NvmapKind_C64_MS2_2CRA=0xCd,
|
||||
NvmapKind_ZF32_X24S8_2CSZV=0xCe,
|
||||
NvmapKind_ZF32_X24S8_MS2_2CSZV=0xCf,
|
||||
NvmapKind_ZF32_X24S8_MS4_2CSZV=0xd0,
|
||||
NvmapKind_ZF32_X24S8_MS8_2CSZV=0xd1,
|
||||
NvmapKind_ZF32_X24S8_MS16_2CSZV=0xd2,
|
||||
NvmapKind_ZF32_X24S8_2CS=0xd3,
|
||||
NvmapKind_ZF32_X24S8_MS2_2CS=0xd4,
|
||||
NvmapKind_ZF32_X24S8_MS4_2CS=0xd5,
|
||||
NvmapKind_ZF32_X24S8_MS8_2CS=0xd6,
|
||||
NvmapKind_ZF32_X24S8_MS16_2CS=0xd7,
|
||||
NvmapKind_C32_2C=0xd8,
|
||||
NvmapKind_C32_2CBR=0xd9,
|
||||
NvmapKind_C32_2CBA=0xda,
|
||||
NvmapKind_C32_2CRA=0xdb,
|
||||
NvmapKind_C32_2BRA=0xdC,
|
||||
NvmapKind_C32_MS2_2C=0xdd,
|
||||
NvmapKind_C32_MS2_2CBR=0xde,
|
||||
NvmapKind_C32_MS2_2CRA=0xCC,
|
||||
NvmapKind_C32_MS4_2C=0xdf,
|
||||
NvmapKind_C32_MS4_2CBR=0xe0,
|
||||
NvmapKind_C32_MS4_2CBA=0xe1,
|
||||
NvmapKind_C32_MS4_2CRA=0xe2,
|
||||
NvmapKind_C32_MS4_2BRA=0xe3,
|
||||
NvmapKind_C32_MS8_MS16_2C=0xe4,
|
||||
NvmapKind_C32_MS8_MS16_2CRA=0xe5,
|
||||
NvmapKind_C64_2C=0xe6,
|
||||
NvmapKind_C64_2CBR=0xe7,
|
||||
NvmapKind_C64_2CBA=0xe8,
|
||||
NvmapKind_C64_2CRA=0xe9,
|
||||
NvmapKind_C64_2BRA=0xea,
|
||||
NvmapKind_C64_MS2_2C=0xeb,
|
||||
NvmapKind_C64_MS2_2CBR=0xeC,
|
||||
NvmapKind_C64_MS4_2C=0xed,
|
||||
NvmapKind_C64_MS4_2CBR=0xee,
|
||||
NvmapKind_C64_MS4_2CBA=0xef,
|
||||
NvmapKind_C64_MS4_2CRA=0xf0,
|
||||
NvmapKind_C64_MS4_2BRA=0xf1,
|
||||
NvmapKind_C64_MS8_MS16_2C=0xf2,
|
||||
NvmapKind_C64_MS8_MS16_2CRA=0xf3,
|
||||
NvmapKind_C128_2C=0xf4,
|
||||
NvmapKind_C128_2CR=0xf5,
|
||||
NvmapKind_C128_MS2_2C=0xf6,
|
||||
NvmapKind_C128_MS2_2CR=0xf7,
|
||||
NvmapKind_C128_MS4_2C=0xf8,
|
||||
NvmapKind_C128_MS4_2CR=0xf9,
|
||||
NvmapKind_C128_MS8_MS16_2C=0xfa,
|
||||
NvmapKind_C128_MS8_MS16_2CR=0xfb,
|
||||
NvmapKind_X8C24=0xfC,
|
||||
NvmapKind_PitchNoSwizzle=0xfd,
|
||||
NvmapKind_Generic_16BX2=0xfe,
|
||||
NvmapKind_Invalid=0xff,
|
||||
} NvmapKind;
|
||||
|
||||
Result nvmapInit();
|
||||
Result nvmapExit();
|
||||
|
||||
Result nvmapCreate(Nvmap* m, size_t size, u32 align, NvmapKind kind);
|
||||
Result nvmapCreateRw(Nvmap* m, size_t size, u32 align, NvmapKind kind);
|
||||
void nvmapFree(Nvmap* m);
|
||||
|
||||
void* nvmapGetAddr(Nvmap* m);
|
||||
@ -17,8 +17,12 @@ Result nvasCreate(NvAddressSpace* a)
|
||||
|
||||
Result nvasClose(NvAddressSpace* a)
|
||||
{
|
||||
nvClose(a->fd);
|
||||
Result rc;
|
||||
|
||||
rc = nvClose(a->fd);
|
||||
a->fd = -1;
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
Result nvasReserveAlign(NvAddressSpace* a, NvPageSize align, u32 pages, NvPageSize page_sz, iova_t* iova_out) {
|
||||
@ -33,6 +37,6 @@ Result nvasReserveFull(NvAddressSpace* a) {
|
||||
return nvasReserveAlign(a, NvPageSize_64K, 0x10000, NvPageSize_64K, NULL);
|
||||
}
|
||||
|
||||
Result nvasMapBuffer(NvAddressSpace* a, Nvmap* buffer, NvmapKind kind, iova_t* iova_out) {
|
||||
Result nvasMapBuffer(NvAddressSpace* a, NvBuffer* buffer, NvBufferKind kind, iova_t* iova_out) {
|
||||
return nvioctlNvhostAsGpu_MapBufferEx(a->fd, 0, kind, buffer->fd, 0, 0, buffer->size, 0, iova_out);
|
||||
}
|
||||
|
||||
@ -3,19 +3,19 @@
|
||||
#include "result.h"
|
||||
#include "services/nv.h"
|
||||
#include "nvidia/ioctl.h"
|
||||
#include "nvidia/nvmap.h"
|
||||
#include "nvidia/buffer.h"
|
||||
|
||||
static u32 g_nvmap_fd;
|
||||
|
||||
Result nvmapInit() {
|
||||
Result nvbufInit() {
|
||||
return nvOpen(&g_nvmap_fd, "/dev/nvmap");
|
||||
}
|
||||
|
||||
Result nvmapExit() {
|
||||
Result nvbufExit() {
|
||||
return nvClose(g_nvmap_fd);
|
||||
}
|
||||
|
||||
static Result _nvmapCreate(Nvmap* m, size_t size, u32 flags, u32 align, NvmapKind kind)
|
||||
static Result _nvbufCreate(NvBuffer* m, size_t size, u32 flags, u32 align, NvBufferKind kind)
|
||||
{
|
||||
Result rc;
|
||||
|
||||
@ -45,15 +45,15 @@ static Result _nvmapCreate(Nvmap* m, size_t size, u32 flags, u32 align, NvmapKin
|
||||
return rc;
|
||||
}
|
||||
|
||||
Result nvmapCreate(Nvmap* m, size_t size, u32 align, NvmapKind kind) {
|
||||
return _nvmapCreate(m, size, 0, align, kind);
|
||||
Result nvbufCreate(NvBuffer* m, size_t size, u32 align, NvBufferKind kind) {
|
||||
return _nvbufCreate(m, size, 0, align, kind);
|
||||
}
|
||||
|
||||
Result nvmapCreateRw(Nvmap* m, size_t size, u32 align, NvmapKind kind) {
|
||||
return _nvmapCreate(m, size, NvmapFlags_Writable, align, kind);
|
||||
Result nvbufCreateRw(NvBuffer* m, size_t size, u32 align, NvBufferKind kind) {
|
||||
return _nvbufCreate(m, size, NvBufferFlags_Writable, align, kind);
|
||||
}
|
||||
|
||||
void nvmapFree(Nvmap* m)
|
||||
void nvbufFree(NvBuffer* m)
|
||||
{
|
||||
free(m->ptr);
|
||||
m->ptr = NULL;
|
||||
@ -62,6 +62,6 @@ void nvmapFree(Nvmap* m)
|
||||
m->fd = -1;
|
||||
}
|
||||
|
||||
void* nvmapGetAddr(Nvmap* m) {
|
||||
void* nvbufGetAddr(NvBuffer* m) {
|
||||
return m->ptr;
|
||||
}
|
||||
@ -2,8 +2,7 @@
|
||||
#include "types.h"
|
||||
#include "result.h"
|
||||
#include "services/nv.h"
|
||||
#include "display/ioctl.h"
|
||||
#include "display/nvioctl.h"
|
||||
#include "nvidia/ioctl.h"
|
||||
|
||||
Result nvioctlNvmap_Create(u32 fd, u32 size, u32 *nvmap_handle) {
|
||||
Result rc=0;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user