diff --git a/nx/include/switch/nvidia/ioctl.h b/nx/include/switch/nvidia/ioctl.h
index f6c31f43..8b7e00cd 100644
--- a/nx/include/switch/nvidia/ioctl.h
+++ b/nx/include/switch/nvidia/ioctl.h
@@ -129,6 +129,12 @@ typedef enum {
     NvZcullConfig_PartOfRegularBuffer = 3
 } NvZcullConfig;
 
+// Used with nvioctlNvhostAsGpu_MapBufferEx().
+typedef enum {
+    NvMapBufferFlags_FixedOffset = 0,
+    NvMapBufferFlags_IsCachable = 4,
+} NvMapBufferFlags;
+
 typedef enum {
     NvErrorType_FifoErrorIdleTimeout=8,
     NvErrorType_GrErrorSwNotify=13,
diff --git a/nx/source/nvidia/address_space.c b/nx/source/nvidia/address_space.c
index c9ab518f..af245f23 100644
--- a/nx/source/nvidia/address_space.c
+++ b/nx/source/nvidia/address_space.c
@@ -45,7 +45,8 @@ Result nvasReserveFull(NvAddressSpace* a) {
 
 Result nvasMapBuffer(NvAddressSpace* a, NvBuffer* buffer, NvBufferKind kind, iova_t* iova_out) {
     // TODO: What is flag==4?
-    return nvioctlNvhostAsGpu_MapBufferEx(a->fd, 4, kind, buffer->fd, 0x10000, 0, 0, 0, iova_out);
+    return nvioctlNvhostAsGpu_MapBufferEx(
+        a->fd, NvMapBufferFlags_IsCachable, kind, buffer->fd, 0x10000, 0, 0, 0, iova_out);
 }
 
 Result nvasBindToChannel(NvAddressSpace* a, NvChannel* channel) {