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nv: Implement ioctl GET_GPU_TIME

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averne 2022-07-02 14:41:49 +02:00 committed by fincs
parent 62755bebe0
commit 8b17648d0b
4 changed files with 33 additions and 0 deletions
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1
nx/include/switch/nvidia/gpu.h
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@ -13,3 +13,4 @@ const u32* nvGpuGetTpcMasks(u32 *num_masks_out);
Result nvGpuZbcGetActiveSlotMask(u32 *out_slot, u32 *out_mask); Result nvGpuZbcGetActiveSlotMask(u32 *out_slot, u32 *out_mask);
Result nvGpuZbcAddColor(const u32 color_l2[4], const u32 color_ds[4], u32 format); Result nvGpuZbcAddColor(const u32 color_l2[4], const u32 color_ds[4], u32 format);
Result nvGpuZbcAddDepth(float depth); Result nvGpuZbcAddDepth(float depth);
Result nvGpuGetTimestamp(u64 *ts);

6
nx/include/switch/nvidia/ioctl.h
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@ -117,6 +117,11 @@ typedef struct {
u32 mask; u32 mask;
} nvioctl_zbc_slot_mask; } nvioctl_zbc_slot_mask;
typedef struct {
u64 timestamp;
u64 reserved;
} nvioctl_gpu_time;
typedef struct { typedef struct {
u32 id; u32 id;
u32 value; u32 value;
@ -246,6 +251,7 @@ Result nvioctlNvhostCtrlGpu_ZbcQueryTable(u32 fd, u32 index, nvioctl_zbc_entry *
Result nvioctlNvhostCtrlGpu_GetCharacteristics(u32 fd, nvioctl_gpu_characteristics *out); Result nvioctlNvhostCtrlGpu_GetCharacteristics(u32 fd, nvioctl_gpu_characteristics *out);
Result nvioctlNvhostCtrlGpu_GetTpcMasks(u32 fd, void *buffer, size_t size); Result nvioctlNvhostCtrlGpu_GetTpcMasks(u32 fd, void *buffer, size_t size);
Result nvioctlNvhostCtrlGpu_ZbcGetActiveSlotMask(u32 fd, nvioctl_zbc_slot_mask *out); Result nvioctlNvhostCtrlGpu_ZbcGetActiveSlotMask(u32 fd, nvioctl_zbc_slot_mask *out);
Result nvioctlNvhostCtrlGpu_GetGpuTime(u32 fd, nvioctl_gpu_time *out);
Result nvioctlNvhostAsGpu_BindChannel(u32 fd, u32 channel_fd); Result nvioctlNvhostAsGpu_BindChannel(u32 fd, u32 channel_fd);
Result nvioctlNvhostAsGpu_AllocSpace(u32 fd, u32 pages, u32 page_size, u32 flags, u64 align_or_offset, u64 *offset); Result nvioctlNvhostAsGpu_AllocSpace(u32 fd, u32 pages, u32 page_size, u32 flags, u64 align_or_offset, u64 *offset);

8
nx/source/nvidia/gpu.c
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@ -90,3 +90,11 @@ Result nvGpuZbcAddDepth(float depth)
memcpy(&depth_int, &depth, sizeof(float)); memcpy(&depth_int, &depth, sizeof(float));
return nvioctlNvhostCtrlGpu_ZbcSetTable(g_ctrlgpu_fd, NULL, NULL, depth_int, 1, NVGPU_ZBC_TYPE_DEPTH); return nvioctlNvhostCtrlGpu_ZbcSetTable(g_ctrlgpu_fd, NULL, NULL, depth_int, 1, NVGPU_ZBC_TYPE_DEPTH);
} }
Result nvGpuGetTimestamp(u64 *ts) {
nvioctl_gpu_time data;
Result rc = nvioctlNvhostCtrlGpu_GetGpuTime(g_ctrlgpu_fd, &data);
if (R_SUCCEEDED(rc) && ts)
*ts = data.timestamp;
return rc;
}

18
nx/source/nvidia/ioctl/nvhost-ctrl-gpu.c
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@ -144,3 +144,21 @@ Result nvioctlNvhostCtrlGpu_ZbcGetActiveSlotMask(u32 fd, nvioctl_zbc_slot_mask *
return rc; return rc;
} }
Result nvioctlNvhostCtrlGpu_GetGpuTime(u32 fd, nvioctl_gpu_time *out) {
Result rc = 0;
struct {
__nv_out nvioctl_gpu_time out;
} data;
memset(&data, 0, sizeof(data));
rc = nvIoctl(fd, _NV_IOWR(0x47, 0x1C, data), &data);
if (R_SUCCEEDED(rc)) {
memcpy(out, &data.out, sizeof(data.out));
}
return rc;
}