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Formatting and adding dma clear

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This commit is contained in:
plutooo 2018-04-15 21:00:30 +02:00
parent 8b5b328a1f
commit 7ca21ae04b
7 changed files with 98 additions and 52 deletions
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20
nx/include/switch/nvidia/cmds/dma.h
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@ -1,13 +1,21 @@
enum { enum {
NvRegDma_Launch = 0xC0, NvRegDma_Launch = 0x0c0,
NvRegDma_SourceAddr = 0x100, NvRegDma_SourceAddr = 0x100,
NvRegDma_DestinationAddr = 0x102, NvRegDma_DestinationAddr = 0x102,
NvRegDma_SourcePitch = 0x104, NvRegDma_SourcePitch = 0x104,
NvRegDma_DestinationPitch = 0x105, NvRegDma_DestinationPitch = 0x105,
NvRegDma_Count = 0x106, NvRegDma_Count = 0x106,
/* NvRegDma_RemapConstant = 0x1c0,
0x1C0 MemsetValue? 1 uint NvRegDma_RemapControl = 0x1c2,
0x1C2 MemsetControl? 1 bitfield Seen: 0x34444 NvRegDma_DestinationWidth = 0x1c4,
0x1C4 MemsetLength? 1 uint In units of 4 bytes. NvRegDma_DestinationHeight = 0x1c5,
*/ };
enum {
NvRegDmaRemapValue_SourceX = 0,
NvRegDmaRemapValue_SourceY = 1,
NvRegDmaRemapValue_SourceZ = 2,
NvRegDmaRemapValue_SourceW = 3,
NvRegDmaRemapValue_Constant0 = 4,
NvRegDmaRemapValue_Constant1 = 5,
}; };

1
nx/include/switch/nvidia/cmds/dma_clear.h Normal file
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@ -0,0 +1 @@
void vnDmaClear32(Vn* vn, iova_t dst, u32 val, size_t size);

20
nx/source/nvidia/cmds/3d_clear.c
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@ -1,17 +1,18 @@
#include <switch.h> #include <switch.h>
#include <string.h> #include <string.h>
void vnClearBuffer( void vnClearBuffer(Vn* vn, NvBuffer* buf, u32 width, u32 height, float colors[4])
Vn* vn, NvBuffer* buf, u32 width, u32 height, float colors[4])
{ {
vnAddCmd(vn, vnAddCmd(
NvIncr(0, NvReg3D_ClearColor, f2i(colors[0]), f2i(colors[1]), f2i(colors[2]), f2i(colors[3])), vn,
NvIncr(0, NvReg3D_ScreenScissorHorizontal, 0 | (width << 16), 0 | (height << 16)), NvIncr(0, NvReg3D_ClearColor, f2i(colors[0]), f2i(colors[1]), f2i(colors[2]), f2i(colors[3])),
NvIncr(0, NvReg3D_RenderTargetControl, (076543210 << 4) | 1)); // bit0 probably enables RT #0 NvIncr(0, NvReg3D_ScreenScissorHorizontal, 0 | (width << 16), 0 | (height << 16)),
NvIncr(0, NvReg3D_RenderTargetControl, (076543210 << 4) | 1)); // bit0 probably enables RT #0
iova_t gpu_addr = nvBufferGetGpuAddr(buf); iova_t gpu_addr = nvBufferGetGpuAddr(buf);
vnAddCmd(vn, vnAddCmd(
NvIncr(0, NvReg3D_RenderTargetNAddr + 0x10*0, vn,
NvIncr(0, NvReg3D_RenderTargetNAddr + 0x10*0,
gpu_addr >> 32, gpu_addr, gpu_addr >> 32, gpu_addr,
width, height, width, height,
0xc2, /* Format */ 0xc2, /* Format */
@ -19,7 +20,8 @@ void vnClearBuffer(
1, /* ArrayMode */ 1, /* ArrayMode */
0, /* Stride */ 0, /* Stride */
0 /* BaseLayer */ 0 /* BaseLayer */
)); )
);
// Disable zeta + multisample // Disable zeta + multisample
vnAddCmd(vn, NvImm(0, 0x54E, 0), NvImm(0, 0x54D, 0)); vnAddCmd(vn, NvImm(0, 0x54E, 0), NvImm(0, 0x54D, 0));

89
nx/source/nvidia/cmds/3d_init.c
View File

@ -4,7 +4,8 @@
Result vnInit3D(Vn* vn) { Result vnInit3D(Vn* vn) {
Result rc; Result rc;
vnAddCmd(vn, vnAddCmd(
vn,
// ??? // ???
NvIncr(0, NvReg3D_MmeShadowScratch(0x1A), 0, 0xffffffff), NvIncr(0, NvReg3D_MmeShadowScratch(0x1A), 0, 0xffffffff),
NvImm(0, NvReg3D_MmeShadowScratch(0x19), 0), NvImm(0, NvReg3D_MmeShadowScratch(0x19), 0),
@ -22,30 +23,34 @@ Result vnInit3D(Vn* vn) {
NvImm(0, 0x1d3, 0x3f), NvImm(0, 0x1d3, 0x3f),
// //
NvIncr(0, NvReg3D_WindowNHorizontal, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), NvIncr(0, NvReg3D_WindowNHorizontal, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
NvImm(0, NvReg3D_ClearFlags, 0x101)); NvImm(0, NvReg3D_ClearFlags, 0x101)
);
size_t i; size_t i;
for (i=0; i<16; i++) { for (i=0; i<16; i++) {
vnAddCmd(vn, NvImm(0, NvReg3D_ScissorEnable(i), 1)); vnAddCmd(vn, NvImm(0, NvReg3D_ScissorEnable(i), 1));
} }
vnAddCmd(vn, NvImm(0, NvReg3D_PrimRestartWithDrawArrays, 1), vnAddCmd(
NvImm(0, NvReg3D_PointRasterRules, 0), vn,
NvImm(0, NvReg3D_LinkedTsc, 0), NvImm(0, NvReg3D_PrimRestartWithDrawArrays, 1),
NvImm(0, NvReg3D_ProvokingVertexLast, 1), NvImm(0, NvReg3D_PointRasterRules, 0),
// ??? NvImm(0, NvReg3D_LinkedTsc, 0),
NvImm(0, 0x54a, 0), NvImm(0, NvReg3D_ProvokingVertexLast, 1),
NvImm(0, 0x400, 0x10), // ???
NvImm(0, 0x86, 0x10), NvImm(0, 0x54a, 0),
NvImm(0, 0x43f, 0x10), NvImm(0, 0x400, 0x10),
NvImm(0, 0x4a4, 0x10), NvImm(0, 0x86, 0x10),
NvImm(0, 0x4b6, 0x10), NvImm(0, 0x43f, 0x10),
NvImm(0, 0x4b7, 0x10), NvImm(0, 0x4a4, 0x10),
// NvImm(0, 0x4b6, 0x10),
NvImm(0, NvReg3D_CallLimitLog, 8), NvImm(0, 0x4b7, 0x10),
// ??? //
NvImm(0, 0x450, 0x10), NvImm(0, NvReg3D_CallLimitLog, 8),
NvImm(0, 0x584, 0xe)); // ???
NvImm(0, 0x450, 0x10),
NvImm(0, 0x584, 0xe)
);
for (i=0; i<16; i++) { for (i=0; i<16; i++) {
vnAddCmd(vn, NvImm(0, NvReg3D_VertexStreamEnableDivisor(i), 0)); vnAddCmd(vn, NvImm(0, NvReg3D_VertexStreamEnableDivisor(i), 0));
@ -79,7 +84,7 @@ Result vnInit3D(Vn* vn) {
NvImm(3, 0xab, 3), // SetOperation? NvImm(3, 0xab, 3), // SetOperation?
NvImm(3, 0xa4, 0), // SetClipEnable NvImm(3, 0xa4, 0), // SetClipEnable
NvImm(3, 0x221, 0x3f) NvImm(3, 0x221, 0x3f)
); );
// TODO: Call macro_14f(0x00418800, 1, 1). // TODO: Call macro_14f(0x00418800, 1, 1).
// TODO: Call macro_14f(0x00419a08, 0, 0x10). // TODO: Call macro_14f(0x00419a08, 0, 0x10).
@ -96,7 +101,7 @@ Result vnInit3D(Vn* vn) {
NvImm(0, NvReg3D_ZcullRegion, 0), NvImm(0, NvReg3D_ZcullRegion, 0),
NvIncr(0, 0x054, 0x49000000, 0x49000001), NvIncr(0, 0x054, 0x49000000, 0x49000001),
NvIncr(0, NvReg3D_MmeShadowScratch(0x18), 0x05000500) NvIncr(0, NvReg3D_MmeShadowScratch(0x18), 0x05000500)
); );
// TODO: Call macro_21d(5, 0x00050000, 0x67); // TODO: Call macro_21d(5, 0x00050000, 0x67);
@ -127,7 +132,8 @@ Result vnInit3D(Vn* vn) {
gpu_addr = nvBufferGetGpuAddr(&vn->const_buffer0); gpu_addr = nvBufferGetGpuAddr(&vn->const_buffer0);
vnAddCmd(vn, vnAddCmd(
vn,
NvIncr( NvIncr(
0, NvReg3D_ConstantBufferSize, 0, NvReg3D_ConstantBufferSize,
0x5f00, 0x5f00,
@ -142,7 +148,8 @@ Result vnInit3D(Vn* vn) {
// Bind const buffer index 2 to differnet buffers (each of size 0x200). // Bind const buffer index 2 to differnet buffers (each of size 0x200).
for (i=0; i<5; i++) { for (i=0; i<5; i++) {
vnAddCmd(vn, vnAddCmd(
vn,
NvIncr(0, NvIncr(0,
NvReg3D_ConstantBufferSize, NvReg3D_ConstantBufferSize,
0x5f00, // Size 0x5f00, // Size
@ -157,7 +164,8 @@ Result vnInit3D(Vn* vn) {
gpu_addr += 0x200; gpu_addr += 0x200;
} }
vnAddCmd(vn, vnAddCmd(
vn,
NvImm(0, NvReg3D_BlendIndependent, 1), NvImm(0, NvReg3D_BlendIndependent, 1),
NvImm(0, NvReg3D_EdgeFlag, 1), NvImm(0, NvReg3D_EdgeFlag, 1),
NvImm(0, NvReg3D_ViewportTransformEnable, 1), NvImm(0, NvReg3D_ViewportTransformEnable, 1),
@ -168,7 +176,8 @@ Result vnInit3D(Vn* vn) {
// Reset all the viewports. // Reset all the viewports.
for (i=0; i<16; i++) { for (i=0; i<16; i++) {
vnAddCmd(vn, vnAddCmd(
vn,
NvIncr(0, NvReg3D_ViewportScaleX(i), NvIncr(0, NvReg3D_ViewportScaleX(i),
f2i(0.5), /* ScaleX */ f2i(0.5), /* ScaleX */
f2i(0.5), /* ScaleY */ f2i(0.5), /* ScaleY */
@ -188,7 +197,8 @@ Result vnInit3D(Vn* vn) {
// Reset all the scissors. // Reset all the scissors.
for (i=0; i<16; i++) { for (i=0; i<16; i++) {
vnAddCmd(vn, vnAddCmd(
vn,
NvIncr(0, NvReg3D_ScissorHorizontal(i), NvIncr(0, NvReg3D_ScissorHorizontal(i),
(0xffff << 16) | 0, /* Horizontal */ (0xffff << 16) | 0, /* Horizontal */
(0xffff << 16) | 0 /* Vertical */ (0xffff << 16) | 0 /* Vertical */
@ -197,20 +207,23 @@ Result vnInit3D(Vn* vn) {
} }
// Setup RAM for macros. // Setup RAM for macros.
vnAddCmd(vn, vnAddCmd(
vn,
NvImm(0, NvReg3D_MmeShadowRamControl, 1), NvImm(0, NvReg3D_MmeShadowRamControl, 1),
NvIncr(0, NvReg3D_MmeShadowScratch(0x1c), NvIncr(0, NvReg3D_MmeShadowScratch(0x1c),
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xffffffff) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xffffffff)
); );
// Reset IndexArrayLimit. // Reset IndexArrayLimit.
vnAddCmd(vn, vnAddCmd(
vn,
NvIncr(0, NvReg3D_IndexArrayLimit, 0xFF, 0xFFFFFFFF), NvIncr(0, NvReg3D_IndexArrayLimit, 0xFF, 0xFFFFFFFF),
NvImm(0, NvReg3D_PrimRestartWithDrawArrays, 0) NvImm(0, NvReg3D_PrimRestartWithDrawArrays, 0)
); );
// More RAM setup. // More RAM setup.
vnAddCmd(vn, vnAddCmd(
vn,
NvIncr(0, NvReg3D_MmeShadowScratch(0x2a), 0x0500055f), NvIncr(0, NvReg3D_MmeShadowScratch(0x2a), 0x0500055f),
NvIncr(0, NvReg3D_MmeShadowScratch(0x2b), 0x05000561), NvIncr(0, NvReg3D_MmeShadowScratch(0x2b), 0x05000561),
NvIncr(0, NvReg3D_MmeShadowScratch(0x2c), 0x05000563), NvIncr(0, NvReg3D_MmeShadowScratch(0x2c), 0x05000563),
@ -233,7 +246,8 @@ Result vnInit3D(Vn* vn) {
NvImm(0, NvReg3D_PointCoordReplace, 4), NvImm(0, NvReg3D_PointCoordReplace, 4),
NvImm(0, NvReg3D_VpPointSize, 1), NvImm(0, NvReg3D_VpPointSize, 1),
NvImm(0, 0x68b, 0), NvImm(0, 0x68b, 0),
NvImm(0, NvReg3D_StencilTwoSideEnable, 1)); NvImm(0, NvReg3D_StencilTwoSideEnable, 1)
);
// NvImm(0, 0xe2a, 0x184)); // MACRO CALL NOT IMPLEMENTED // NvImm(0, 0xe2a, 0x184)); // MACRO CALL NOT IMPLEMENTED
// TODO: Call macro_206(0x184); // TODO: Call macro_206(0x184);
@ -243,7 +257,7 @@ Result vnInit3D(Vn* vn) {
vn, vn,
NvImm(0, NvReg3D_ZetaArrayMode, 1), NvImm(0, NvReg3D_ZetaArrayMode, 1),
NvImm(0, NvReg3D_ConservativeRaster, 0), NvImm(0, NvReg3D_ConservativeRaster, 0),
); );
// TODO: Call macro_14f(0x00418800, 0, 0x01800000); // TODO: Call macro_14f(0x00418800, 0, 0x01800000);
@ -259,7 +273,8 @@ Result vnInit3D(Vn* vn) {
//vnAddCmd(vn, NvIncr(0, NvReg3D_CodeAddr, 4, 0x00000000)); //vnAddCmd(vn, NvIncr(0, NvReg3D_CodeAddr, 4, 0x00000000));
vnAddCmd(vn, vnAddCmd(
vn,
NvImm(0, NvReg3D_MmeShadowScratch(0x27), 0x230), NvImm(0, NvReg3D_MmeShadowScratch(0x27), 0x230),
NvImm(0, NvReg3D_MmeShadowScratch(0x23), 0x430), NvImm(0, NvReg3D_MmeShadowScratch(0x23), 0x430),
NvImm(0, 0x5ad, 0) NvImm(0, 0x5ad, 0)
@ -289,7 +304,8 @@ Result vnInit3D(Vn* vn) {
// TODO: Call macro_14f(0x00418e6c, 0x644, 0xffff); // TODO: Call macro_14f(0x00418e6c, 0x644, 0xffff);
// Setting up TiledCache and other stuff. // Setting up TiledCache and other stuff.
vnAddCmd(vn, vnAddCmd(
vn,
NvImm(0, 0x3d8, 0), NvImm(0, 0x3d8, 0),
NvIncr(0, 0x3d9, 0x00800080), NvIncr(0, 0x3d9, 0x00800080),
NvIncr(0, 0x3da, 0x1109), NvIncr(0, 0x3da, 0x1109),
@ -318,16 +334,19 @@ Result vnInit3D(Vn* vn) {
*/ */
// Flush texture info cache. // Flush texture info cache.
vnAddCmd(vn, vnAddCmd(
vn,
NvImm(0, 0x4a2, 0), NvImm(0, 0x4a2, 0),
NvImm(0, 0x369, 0x11), NvImm(0, 0x369, 0x11),
NvImm(0, 0x50a, 0), NvImm(0, 0x50a, 0),
NvImm(0, 0x509, 0) NvImm(0, 0x509, 0)
); );
vnAddCmd(vn, vnAddCmd(
vn,
NvIncr(0, 0x1e9, 0x7ff8), NvIncr(0, 0x1e9, 0x7ff8),
NvIncr(0, 0x1ea, 0x7ffc) NvIncr(0, 0x1ea, 0x7ffc)
); );
return 0; return 0;
} }

3
nx/source/nvidia/cmds/3d_rendertarget.c
View File

@ -22,6 +22,7 @@ void vnSetRenderTargets(Vn* vn, VnRenderTargetConfig* targets, size_t num_target
0, 0,
targets[i].width, // TODO: Round up to power of 2? targets[i].width, // TODO: Round up to power of 2?
0 0
)); )
);
} }
} }

3
nx/source/nvidia/cmds/common.c
View File

@ -17,7 +17,8 @@ Result vnInit(Vn* vn, NvGpu* parent)
NvIncr(1, NvCmdCommon_BindObject, NvClassNumber_Compute), NvIncr(1, NvCmdCommon_BindObject, NvClassNumber_Compute),
NvIncr(2, NvCmdCommon_BindObject, NvClassNumber_Kepler), NvIncr(2, NvCmdCommon_BindObject, NvClassNumber_Kepler),
NvIncr(3, NvCmdCommon_BindObject, NvClassNumber_2D), NvIncr(3, NvCmdCommon_BindObject, NvClassNumber_2D),
NvIncr(4, NvCmdCommon_BindObject, NvClassNumber_DMA)); NvIncr(4, NvCmdCommon_BindObject, NvClassNumber_DMA)
);
return rc; return rc;
} }

14
nx/source/nvidia/cmds/dma_memset.c
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@ -0,0 +1,14 @@
#include <switch.h>
#include <string.h>
void vnDmaClear32(Vn* vn, iova_t dst, u32 val, size_t size) {
vnAddCmd(
vn,
NvIncr(4, NvRegDma_RemapConstant, val),
NvIncr(4, NvRegDma_RemapControl, 0x30000 | (NvRegDmaRemapValue_Constant0 * 0x1111)),
NvIncr(4, NvRegDma_SourceAddr, dst>>32, dst, dst>>32, dst),
NvIncr(4, NvRegDma_DestinationWidth, size/4, 1),
NvIncr(4, NvRegDma_Count, size),
NvIncr(4, NvRegDma_Launch, 0x586)
);
}