From 320b054f6ea684549909fa90c2954f21f50abe26 Mon Sep 17 00:00:00 2001
From: fincs <fincs@devkitpro.org>
Date: Fri, 17 May 2019 21:15:57 +0200
Subject: [PATCH] Added nvGpu* wrapper functions for zcull/zbc/tpc ioctls

---
 nx/include/switch/nvidia/gpu.h |  6 +++++
 nx/source/nvidia/gpu.c         | 47 +++++++++++++++++++++++++++++++++-
 2 files changed, 52 insertions(+), 1 deletion(-)

diff --git a/nx/include/switch/nvidia/gpu.h b/nx/include/switch/nvidia/gpu.h
index 06fbe513..213c4c13 100644
--- a/nx/include/switch/nvidia/gpu.h
+++ b/nx/include/switch/nvidia/gpu.h
@@ -7,3 +7,9 @@ void nvGpuExit(void);
 
 const nvioctl_gpu_characteristics* nvGpuGetCharacteristics(void);
 u32 nvGpuGetZcullCtxSize(void);
+const nvioctl_zcull_info* nvGpuGetZcullInfo(void);
+const u32* nvGpuGetTpcMasks(u32 *num_masks_out);
+
+Result nvGpuZbcGetActiveSlotMask(u32 *out_slot, u32 *out_mask);
+Result nvGpuZbcAddColor(u32 color_l2[4], u32 color_ds[4], u32 format);
+Result nvGpuZbcAddDepth(float depth);
diff --git a/nx/source/nvidia/gpu.c b/nx/source/nvidia/gpu.c
index 76f9b1ff..558922fb 100644
--- a/nx/source/nvidia/gpu.c
+++ b/nx/source/nvidia/gpu.c
@@ -1,4 +1,4 @@
-#include <malloc.h>
+#include <string.h>
 #include "types.h"
 #include "result.h"
 #include "arm/atomics.h"
@@ -7,11 +7,16 @@
 #include "nvidia/ioctl.h"
 #include "nvidia/gpu.h"
 
+// Official software hardcodes this for both Tegra X1 (and even K1).
+#define NUM_TPC_MASKS 1
+
 static u32 g_ctrlgpu_fd = -1;
 static u64 g_refCnt;
 
 static nvioctl_gpu_characteristics g_gpu_characteristics;
 static u32 g_zcull_ctx_size;
+static nvioctl_zcull_info g_zcull_info;
+static u32 g_tpc_masks[NUM_TPC_MASKS];
 
 Result nvGpuInit(void)
 {
@@ -31,6 +36,12 @@ Result nvGpuInit(void)
     if (R_SUCCEEDED(rc))
         rc = nvioctlNvhostCtrlGpu_ZCullGetCtxSize(g_ctrlgpu_fd, &g_zcull_ctx_size);
 
+    if (R_SUCCEEDED(rc))
+        rc = nvioctlNvhostCtrlGpu_ZCullGetInfo(g_ctrlgpu_fd, &g_zcull_info);
+
+    if (R_SUCCEEDED(rc))
+        rc = nvioctlNvhostCtrlGpu_GetTpcMasks(g_ctrlgpu_fd, g_tpc_masks, sizeof(g_tpc_masks));
+
     if (R_FAILED(rc))
         nvGpuExit();
 
@@ -56,3 +67,37 @@ u32 nvGpuGetZcullCtxSize(void)
 {
     return g_zcull_ctx_size;
 }
+
+const nvioctl_zcull_info* nvGpuGetZcullInfo(void)
+{
+    return &g_zcull_info;
+}
+
+const u32* nvGpuGetTpcMasks(u32 *num_masks_out)
+{
+    if (num_masks_out) *num_masks_out = NUM_TPC_MASKS;
+    return g_tpc_masks;
+}
+
+Result nvGpuZbcGetActiveSlotMask(u32 *out_slot, u32 *out_mask)
+{
+    nvioctl_zbc_slot_mask data;
+    Result rc = nvioctlNvhostCtrlGpu_ZbcGetActiveSlotMask(g_ctrlgpu_fd, &data);
+    if (R_SUCCEEDED(rc)) {
+        if (out_slot) *out_slot = data.slot;
+        if (out_mask) *out_mask = data.mask;
+    }
+    return rc;
+}
+
+Result nvGpuZbcAddColor(u32 color_l2[4], u32 color_ds[4], u32 format)
+{
+    return nvioctlNvhostCtrlGpu_ZbcSetTable(g_ctrlgpu_fd, color_ds, color_l2, 0, format, NVGPU_ZBC_TYPE_COLOR);
+}
+
+Result nvGpuZbcAddDepth(float depth)
+{
+    u32 depth_int;
+    memcpy(&depth_int, &depth, sizeof(float));
+    return nvioctlNvhostCtrlGpu_ZbcSetTable(g_ctrlgpu_fd, NULL, NULL, depth_int, 1, NVGPU_ZBC_TYPE_DEPTH);
+}