From 0c19c1738cb5447698349b11dbd49ca7a0621c73 Mon Sep 17 00:00:00 2001 From: yellows8 Date: Sun, 12 Nov 2017 23:32:50 -0500 Subject: [PATCH] Added nvioctl. --- nx/include/switch.h | 1 + nx/include/switch/gfx/nvioctl.h | 40 +++++++++++++++++++++++++++++++++ nx/source/gfx/nvioctl.c | 24 ++++++++++++++++++++ 3 files changed, 65 insertions(+) create mode 100644 nx/include/switch/gfx/nvioctl.h create mode 100644 nx/source/gfx/nvioctl.c diff --git a/nx/include/switch.h b/nx/include/switch.h index 377c7a12..9f7fcaff 100644 --- a/nx/include/switch.h +++ b/nx/include/switch.h @@ -40,6 +40,7 @@ extern "C" { #include #include #include +#include #include #include diff --git a/nx/include/switch/gfx/nvioctl.h b/nx/include/switch/gfx/nvioctl.h new file mode 100644 index 00000000..1e1a7f2e --- /dev/null +++ b/nx/include/switch/gfx/nvioctl.h @@ -0,0 +1,40 @@ +typedef struct { + u32 arch; // 0x120 (NVGPU_GPU_ARCH_GM200) + u32 impl; // 0xB (NVGPU_GPU_IMPL_GM20B) + u32 rev; // 0xA1 (Revision A1) + u32 num_gpc; // 0x1 + u64 L2_cache_size; // 0x40000 + u64 on_board_video_memory_size; // 0x0 (not used) + u32 num_tpc_per_gpc; // 0x2 + u32 bus_type; // 0x20 (NVGPU_GPU_BUS_TYPE_AXI) + u32 big_page_size; // 0x20000 + u32 compression_page_size; // 0x20000 + u32 pde_coverage_bit_count; // 0x1B + u32 available_big_page_sizes; // 0x30000 + u32 gpc_mask; // 0x1 + u32 sm_arch_sm_version; // 0x503 (Maxwell Generation 5.0.3?) + u32 sm_arch_spa_version; // 0x503 (Maxwell Generation 5.0.3?) + u32 sm_arch_warp_count; // 0x80 + u32 gpu_va_bit_count; // 0x28 + u32 reserved; // NULL + u64 flags; // 0x55 + u32 twod_class; // 0x902D (FERMI_TWOD_A) + u32 threed_class; // 0xB197 (MAXWELL_B) + u32 compute_class; // 0xB1C0 (MAXWELL_COMPUTE_B) + u32 gpfifo_class; // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A) + u32 inline_to_memory_class; // 0xA140 (KEPLER_INLINE_TO_MEMORY_B) + u32 dma_copy_class; // 0xB0B5 (MAXWELL_DMA_COPY_A) + u32 max_fbps_count; // 0x1 + u32 fbp_en_mask; // 0x0 (disabled) + u32 max_ltc_per_fbp; // 0x2 + u32 max_lts_per_ltc; // 0x1 + u32 max_tex_per_tpc; // 0x0 (not supported) + u32 max_gpc_count; // 0x1 + u32 rop_l2_en_mask_0; // 0x21D70 (fuse_status_opt_rop_l2_fbp_r) + u32 rop_l2_en_mask_1; // 0x0 + u64 chipname; // 0x6230326D67 ("gm20b") + u64 gr_compbit_store_base_hw; // 0x0 (not supported) + } gpu_characteristics; + +Result nvioctlNvhostCtrlGpu_GetCharacteristics(u32 fd, gpu_characteristics *out); + diff --git a/nx/source/gfx/nvioctl.c b/nx/source/gfx/nvioctl.c new file mode 100644 index 00000000..166fb115 --- /dev/null +++ b/nx/source/gfx/nvioctl.c @@ -0,0 +1,24 @@ +#include +#include + +Result nvioctlNvhostCtrlGpu_GetCharacteristics(u32 fd, gpu_characteristics *out) { + Result rc = 0; + + struct { + u64 gpu_characteristics_buf_size; // in/out (must not be NULL, but gets overwritten with 0xA0=max_size) + u64 gpu_characteristics_buf_addr; // in (ignored, but must not be NULL) + gpu_characteristics gc; // out + } data; + + memset(&data, 0, sizeof(data)); + data.gpu_characteristics_buf_size = sizeof(gpu_characteristics); + data.gpu_characteristics_buf_addr = 1; + + rc = nvIoctl(fd, _IOWR(0x47, 0x05, data), &data); + if (R_FAILED(rc)) return rc; + + memcpy(out, &data.gc, sizeof(gpu_characteristics)); + + return rc; +} +