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			47 lines
		
	
	
		
			2.0 KiB
		
	
	
	
		
			C++
		
	
	
	
	
	
			
		
		
	
	
			47 lines
		
	
	
		
			2.0 KiB
		
	
	
	
		
			C++
		
	
	
	
	
	
| /*
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|  * Copyright (c) 2018-2020 Atmosphère-NX
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|  *
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|  * This program is free software; you can redistribute it and/or modify it
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|  * under the terms and conditions of the GNU General Public License,
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|  * version 2, as published by the Free Software Foundation.
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|  *
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|  * This program is distributed in the hope it will be useful, but WITHOUT
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|  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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|  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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|  * more details.
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|  *
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|  * You should have received a copy of the GNU General Public License
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|  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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|  */
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| #include <exosphere.hpp>
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| #include "warmboot_clkrst.hpp"
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| 
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| namespace ams::warmboot {
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| 
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|     namespace {
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| 
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|         constexpr inline const uintptr_t CLKRST   = secmon::MemoryRegionPhysicalDeviceClkRst.GetAddress();
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|         constexpr inline const uintptr_t PMC      = secmon::MemoryRegionPhysicalDevicePmc.GetAddress();
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|         constexpr inline const uintptr_t TIMER    = secmon::MemoryRegionPhysicalDeviceTimer.GetAddress();
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| 
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|     }
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| 
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|     void ConfigureOscillators() {
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|         /* Enable the crystal oscillator, and copy the drive strength from pmc. */
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|         const auto xofs = reg::GetValue(PMC + APBDEV_PMC_OSC_EDPD_OVER, PMC_REG_BITS_MASK(OSC_EDPD_OVER_XOFS));
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| 
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|         reg::ReadWrite(CLKRST + CLK_RST_CONTROLLER_OSC_CTRL, CLK_RST_REG_BITS_ENUM (OSC_CTRL_XOE, ENABLE),
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|                                                              CLK_RST_REG_BITS_VALUE(OSC_CTRL_XOFS,  xofs));
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| 
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|         /* Configure CLK_M_DIVISOR to 2. */
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|         reg::Write(CLKRST + CLK_RST_CONTROLLER_SPARE_REG0, CLK_RST_REG_BITS_ENUM(SPARE_REG0_CLK_M_DIVISOR, CLK_M_DIVISOR2));
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|         reg::Read(CLKRST + CLK_RST_CONTROLLER_SPARE_REG0);
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| 
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|         /* Restore TIMERUS config to 19.2 MHz. */
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|         reg::Write(TIMER + TIMERUS_USEC_CFG, TIMER_REG_BITS_VALUE(USEC_CFG_USEC_DIVIDEND,  5 - 1),
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|                                              TIMER_REG_BITS_VALUE(USEC_CFG_USEC_DIVISOR,  96 - 1));
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| 
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|     }
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| 
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| }
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