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			106 lines
		
	
	
		
			2.8 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
	
	
			
		
		
	
	
			106 lines
		
	
	
		
			2.8 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
	
	
| /*
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|  * Copyright (c) Atmosphère-NX
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|  *
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|  * This program is free software; you can redistribute it and/or modify it
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|  * under the terms and conditions of the GNU General Public License,
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|  * version 2, as published by the Free Software Foundation.
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|  *
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|  * This program is distributed in the hope it will be useful, but WITHOUT
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|  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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|  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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|  * more details.
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|  *
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|  * You should have received a copy of the GNU General Public License
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|  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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|  */
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| 
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| /* For some reason GAS doesn't know about it, even with .cpu cortex-a57 */
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| #define cpuactlr_el1 s3_1_c15_c2_0
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| #define cpuectlr_el1 s3_1_c15_c2_1
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| 
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| .macro      RESET_CORE
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|     mov  x0, #(1 << 63)
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|     msr  cpuactlr_el1, x0 /* disable regional clock gating */
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|     isb
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|     mov  x0, #3
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|     msr  rmr_el3, x0
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|     isb
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|     dsb  sy
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|     /* Nintendo forgot to copy-paste the branch instruction below. */
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|     1:
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|         wfi
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|         b 1b
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| .endm
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| 
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| .macro      ERRATUM_INVALIDATE_BTB_AT_BOOT
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| /* Nintendo copy-pasted https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/nvidia/tegra/common/aarch64/tegra_helpers.S#L312 */
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|         /*
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|         * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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|         *
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|         * SPDX-License-Identifier: BSD-3-Clause
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|         */
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|     /* The following comments are mine. */
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| 
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|     /*
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|         Enable invalidates of branch target buffer, then flush
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|         the entire instruction cache at the local level, and
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|         with the reg change, the branch target buffer, then disable
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|         invalidates of the branch target buffer again.
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|     */
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|     mrs  x0, cpuactlr_el1
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|     orr  x0, x0, #1
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|     msr  cpuactlr_el1, x0
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| 
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|     dsb  sy
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|     isb
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|     ic   iallu
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|     dsb  sy
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|     isb
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| 
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|     mrs  x0, cpuactlr_el1
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|     bic  x0, x0, #1
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|     msr  cpuactlr_el1, x0
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| 
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| .rept 7
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|     nop                     /* wait long enough for the write to cpuactlr_el1 to have completed */
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| .endr
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| 
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|     /* if the OS lock is set, disable it and request a warm reset */
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|     mrs  x0, oslsr_el1
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|     ands x0, x0, #2
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|     b.eq 2f
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|     mov  x0, xzr
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|     msr  oslar_el1, x0
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| 
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|     RESET_CORE
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| 
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| .rept 65
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|     nop                     /* guard against speculative excecution */
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| .endr
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| 
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|     2:
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|     /* set the OS lock */
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|     mov  x0, #1
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|     msr  oslar_el1, x0
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| .endm
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| 
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| .section    .crt0.text.start, "ax", %progbits
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| .align      6
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| .global     _start
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| _start:
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|     /* mask all interrupts */
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|     msr daifset, #0xF
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| 
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|     /* Fixup hardware erratum */
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|     ERRATUM_INVALIDATE_BTB_AT_BOOT
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| 
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|     /* Set the stack pointer to a temporary location. */
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|     ldr x20, =0x7C020000
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|     mov sp, x20
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| 
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|     adr x0, program_lz4
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|     adr x1, boot_code_lz4
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| 
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|     /* Uncompress the program and iram boot code images. */
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|     b _ZN3ams6secmon6loader20UncompressAndExecuteEPKvS3_
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