mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
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90 lines
3.7 KiB
C++
90 lines
3.7 KiB
C++
/*
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* Copyright (c) Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#if defined(ATMOSPHERE_IS_STRATOSPHERE)
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#include <stratosphere.hpp>
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#else
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#include <vapours.hpp>
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#endif
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namespace ams::dd::impl {
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void StoreDataCacheImpl(void *addr, size_t size) {
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#if defined(ATMOSPHERE_ARCH_ARM64)
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/* On aarch64, we can use cache maintenance instructions. */
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/* Get cache line size. */
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uintptr_t ctr_el0 = 0;
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__asm__ __volatile__("mrs %[ctr_el0], ctr_el0" : [ctr_el0]"=r"(ctr_el0));
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const uintptr_t cache_line_size = 4 << ((ctr_el0 >> 16) & 0xF);
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/* Invalidate the cache. */
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const uintptr_t start_addr = reinterpret_cast<uintptr_t>(addr) & ~(cache_line_size - 1);
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const uintptr_t end_addr = reinterpret_cast<uintptr_t>(addr) + size;
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for (uintptr_t cur = start_addr; cur < end_addr; cur += cache_line_size) {
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__asm__ __volatile__("dc cvac, %[cur]" : : [cur]"r"(cur));
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}
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/* Add a memory barrier. */
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__asm__ __volatile__("dsb sy" ::: "memory");
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#elif defined(ATMOSPHERE_ARCH_X64) || defined(ATMOSPHERE_ARCH_X86)
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/* Don't do anything, cache maintenance isn't available/relevant to userland. */
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AMS_UNUSED(addr, size);
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#else
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#error "Unknown architecture for linux dd::StoreDataCacheImpl"
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#endif
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}
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void FlushDataCacheImpl(void *addr, size_t size) {
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#if defined(ATMOSPHERE_ARCH_ARM64)
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/* On aarch64, we can use cache maintenance instructions. */
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/* Get cache line size. */
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uintptr_t ctr_el0 = 0;
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__asm__ __volatile__("mrs %[ctr_el0], ctr_el0" : [ctr_el0]"=r"(ctr_el0));
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const uintptr_t cache_line_size = 4 << ((ctr_el0 >> 16) & 0xF);
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/* Invalidate the cache. */
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const uintptr_t start_addr = reinterpret_cast<uintptr_t>(addr) & ~(cache_line_size - 1);
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const uintptr_t end_addr = reinterpret_cast<uintptr_t>(addr) + size;
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for (uintptr_t cur = start_addr; cur < end_addr; cur += cache_line_size) {
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__asm__ __volatile__("dc civac, %[cur]" : : [cur]"r"(cur));
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}
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/* Add a memory barrier. */
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__asm__ __volatile__("dsb sy" ::: "memory");
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#elif defined(ATMOSPHERE_ARCH_X64) || defined(ATMOSPHERE_ARCH_X86)
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/* Don't do anything, cache maintenance isn't available/relevant to userland. */
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AMS_UNUSED(addr, size);
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#else
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#error "Unknown architecture for linux dd::FlushDataCacheImpl"
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#endif
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}
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void InvalidateDataCacheImpl(void *addr, size_t size) {
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#if defined(ATMOSPHERE_ARCH_ARM64)
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/* Just perform a flush, which is clean + invalidate. */
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return FlushDataCacheImpl(addr, size);
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#elif defined(ATMOSPHERE_ARCH_X64) || defined(ATMOSPHERE_ARCH_X86)
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/* Don't do anything, cache maintenance isn't available/relevant to userland. */
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AMS_UNUSED(addr, size);
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#else
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#error "Unknown architecture for linux dd::InvalidateDataCacheImpl"
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#endif
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}
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}
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