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https://github.com/Atmosphere-NX/Atmosphere.git
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80 lines
2.9 KiB
C
80 lines
2.9 KiB
C
/*
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* Copyright (c) 2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "memory_map.h"
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#include "../../utils.h"
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#include "../../mmu.h"
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#include "../../core_ctx.h"
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// Tegra PA size is 36-bit... should we limit ourselves to 34?
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// i.e. 14GB of dram max
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#define ADDRSPACESZ 36
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#define ADDRSPACESZ2 ADDRSPACESZ
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static ALIGN(0x1000) u64 g_ttbl[BIT(ADDRSPACESZ - 30)] = {0};
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static ALIGN(0x1000) u64 g_vttbl[BIT(ADDRSPACESZ2 - 30)] = {0};
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static TEMPORARY ALIGN(0x1000) u64 g_vttbl_l2_mmio_0[512] = {0};
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static TEMPORARY ALIGN(0x1000) u64 g_vttbl_l3_0[512] = {0};
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static inline void identityMapL1(u64 *tbl, uintptr_t addr, size_t size, u64 attribs)
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{
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mmu_map_block_range(1, tbl, addr, addr, size, attribs | MMU_PTE_BLOCK_INNER_SHAREBLE);
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}
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static inline void identityMapL2(u64 *tbl, uintptr_t addr, size_t size, u64 attribs)
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{
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mmu_map_block_range(2, tbl, addr, addr, size, attribs | MMU_PTE_BLOCK_INNER_SHAREBLE);
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}
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static inline void identityMapL3(u64 *tbl, uintptr_t addr, size_t size, u64 attribs)
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{
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mmu_map_block_range(3, tbl, addr, addr, size, attribs | MMU_PTE_BLOCK_INNER_SHAREBLE);
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}
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uintptr_t configureMemoryMap(u32 *addrSpaceSize)
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{
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*addrSpaceSize = ADDRSPACESZ;
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if (currentCoreCtx->isBootCore && !currentCoreCtx->warmboot) {
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identityMapL1(g_ttbl, 0x00000000ull, 2 * BITL(30), ATTRIB_MEMTYPE_DEVICE);
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identityMapL1(g_ttbl, 0x80000000ull, (BITL(ADDRSPACESZ - 30) - 2ull) << 30, ATTRIB_MEMTYPE_NORMAL);
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}
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return (uintptr_t)g_ttbl;
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}
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uintptr_t configureStage2MemoryMap(u32 *addrSpaceSize)
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{
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*addrSpaceSize = ADDRSPACESZ2;
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static const u64 devattrs = MMU_S2AP_RW | MMU_MEMATTR_DEVICE_NGNRE;
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static const u64 unchanged = MMU_S2AP_RW | MMU_MEMATTR_NORMAL_CACHEABLE_OR_UNCHANGED;
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if (currentCoreCtx->isBootCore) {
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identityMapL1(g_vttbl, 0x00000000ull, BITL(30), unchanged);
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identityMapL1(g_vttbl, 0x80000000ull, (BITL(ADDRSPACESZ2 - 30) - 2ull) << 30, unchanged);
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mmu_map_table(1, g_vttbl, 0x40000000ull, g_vttbl_l2_mmio_0, 0);
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identityMapL2(g_vttbl_l2_mmio_0, 0x40000000ull, BITL(30), unchanged);
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mmu_map_table(2, g_vttbl_l2_mmio_0, 0x50000000ull, g_vttbl_l3_0, 0);
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identityMapL3(g_vttbl_l3_0, 0x00000000ull, BITL(21), unchanged);
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// GICv2 CPU -> vCPU interface
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mmu_map_page_range(g_vttbl_l3_0, 0x50042000ull, 0x50046000ull, 0x2000ull, devattrs);
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}
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return (uintptr_t)g_vttbl;
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}
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