mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2025-11-16 17:11:18 +01:00
3bc1951820
NOTE: This work is not yet fully complete; kernel is done, but it was taking an exceedingly long time to get through libstratosphere. Thus, I've temporarily added -Wno-error=unused-result for libstratosphere/stratosphere. All warnings should be fixed to do the same thing Nintendo does as relevant, but this is taking a phenomenally long time and is not actually the most important work to do, so it can be put off for some time to prioritize other tasks for 21.0.0 support.
529 lines
22 KiB
C++
529 lines
22 KiB
C++
/*
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* Copyright (c) Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <mesosphere.hpp>
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namespace ams::kern::arch::arm64::cpu {
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/* Declare prototype to be implemented in asm. */
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void SynchronizeAllCoresImpl(s32 *sync_var, s32 num_cores);
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namespace {
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ALWAYS_INLINE void SetEventLocally() {
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__asm__ __volatile__("sevl" ::: "memory");
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}
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ALWAYS_INLINE void WaitForEvent() {
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__asm__ __volatile__("wfe" ::: "memory");
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}
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class KScopedCoreMigrationDisable {
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public:
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ALWAYS_INLINE KScopedCoreMigrationDisable() { GetCurrentThread().DisableCoreMigration(); }
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ALWAYS_INLINE ~KScopedCoreMigrationDisable() { GetCurrentThread().EnableCoreMigration(); }
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};
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class KScopedCacheMaintenance {
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private:
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bool m_active;
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public:
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ALWAYS_INLINE KScopedCacheMaintenance() {
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__asm__ __volatile__("" ::: "memory");
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if (m_active = !GetCurrentThread().IsInCacheMaintenanceOperation(); m_active) {
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GetCurrentThread().SetInCacheMaintenanceOperation();
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}
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}
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ALWAYS_INLINE ~KScopedCacheMaintenance() {
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if (m_active) {
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GetCurrentThread().ClearInCacheMaintenanceOperation();
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}
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__asm__ __volatile__("" ::: "memory");
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}
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};
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/* Nintendo registers a handler for a SGI on thread termination, but does not handle anything. */
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/* This is sufficient, because post-interrupt scheduling is all they really intend to occur. */
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class KThreadTerminationInterruptHandler : public KInterruptHandler {
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public:
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constexpr KThreadTerminationInterruptHandler() : KInterruptHandler() { /* ... */ }
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virtual KInterruptTask *OnInterrupt(s32 interrupt_id) override {
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MESOSPHERE_UNUSED(interrupt_id);
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return nullptr;
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}
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};
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class KPerformanceCounterInterruptHandler : public KInterruptHandler {
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private:
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static constinit inline KLightLock s_lock;
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private:
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u64 m_counter;
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s32 m_which;
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bool m_done;
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public:
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constexpr KPerformanceCounterInterruptHandler() : KInterruptHandler(), m_counter(), m_which(), m_done() { /* ... */ }
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static KLightLock &GetLock() { return s_lock; }
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void Setup(s32 w) {
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m_done = false;
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m_which = w;
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}
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void Wait() {
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while (!m_done) {
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cpu::Yield();
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}
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}
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u64 GetCounter() const { return m_counter; }
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/* Nintendo misuses this per their own API, but it's functional. */
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virtual KInterruptTask *OnInterrupt(s32 interrupt_id) override {
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MESOSPHERE_UNUSED(interrupt_id);
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if (m_which < 0) {
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m_counter = cpu::GetCycleCounter();
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} else {
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m_counter = cpu::GetPerformanceCounter(m_which);
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}
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DataMemoryBarrierInnerShareable();
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m_done = true;
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return nullptr;
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}
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};
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class KCoreBarrierInterruptHandler : public KInterruptHandler {
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private:
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util::Atomic<u64> m_target_cores;
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KLightLock m_lock;
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public:
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constexpr KCoreBarrierInterruptHandler() : KInterruptHandler(), m_target_cores(0), m_lock() { /* ... */ }
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virtual KInterruptTask *OnInterrupt(s32 interrupt_id) override {
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MESOSPHERE_UNUSED(interrupt_id);
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m_target_cores &= ~(1ul << GetCurrentCoreId());
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return nullptr;
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}
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void SynchronizeCores(u64 core_mask) {
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/* Acquire exclusive access to ourselves. */
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KScopedLightLock lk(m_lock);
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/* If necessary, force synchronization with other cores. */
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if (const u64 other_cores_mask = core_mask & ~(1ul << GetCurrentCoreId()); other_cores_mask != 0) {
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/* Send an interrupt to the other cores. */
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m_target_cores = other_cores_mask;
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cpu::DataSynchronizationBarrierInnerShareable();
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Kernel::GetInterruptManager().SendInterProcessorInterrupt(KInterruptName_CoreBarrier, other_cores_mask);
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/* Wait for all cores to acknowledge. */
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{
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u64 v;
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__asm__ __volatile__("ldaxr %[v], %[p]\n"
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"cbz %[v], 1f\n"
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"0:\n"
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"wfe\n"
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"ldaxr %[v], %[p]\n"
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"cbnz %[v], 0b\n"
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"1:\n"
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: [v]"=&r"(v)
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: [p]"Q"(*reinterpret_cast<u64 *>(std::addressof(m_target_cores)))
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: "memory");
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}
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}
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}
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};
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class KCacheHelperInterruptHandler : public KInterruptHandler {
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private:
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static constexpr s32 ThreadPriority = 8;
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public:
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enum class Operation {
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Idle,
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InstructionMemoryBarrier,
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StoreDataCache,
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FlushDataCache,
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};
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private:
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KLightLock m_lock;
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KLightLock m_cv_lock;
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KLightConditionVariable m_cv;
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util::Atomic<u64> m_target_cores;
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volatile Operation m_operation;
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private:
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static void ThreadFunction(uintptr_t _this) {
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reinterpret_cast<KCacheHelperInterruptHandler *>(_this)->ThreadFunctionImpl();
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}
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void ThreadFunctionImpl() {
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const u64 core_mask = (1ul << GetCurrentCoreId());
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while (true) {
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/* Wait for a request to come in. */
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{
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KScopedLightLock lk(m_cv_lock);
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while ((m_target_cores.Load() & core_mask) == 0) {
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m_cv.Wait(std::addressof(m_cv_lock));
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}
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}
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/* Process the request. */
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this->ProcessOperation();
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/* Broadcast, if there's nothing pending. */
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{
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KScopedLightLock lk(m_cv_lock);
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m_target_cores &= ~core_mask;
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if (m_target_cores.Load() == 0) {
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m_cv.Broadcast();
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}
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}
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}
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}
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void ProcessOperation();
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public:
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constexpr KCacheHelperInterruptHandler() : KInterruptHandler(), m_lock(), m_cv_lock(), m_cv(util::ConstantInitialize), m_target_cores(0), m_operation(Operation::Idle) { /* ... */ }
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void Initialize(s32 core_id) {
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/* Reserve a thread from the system limit. */
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MESOSPHERE_ABORT_UNLESS(Kernel::GetSystemResourceLimit().Reserve(ams::svc::LimitableResource_ThreadCountMax, 1));
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/* Create a new thread. */
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KThread *new_thread = KThread::Create();
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MESOSPHERE_ABORT_UNLESS(new_thread != nullptr);
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MESOSPHERE_R_ABORT_UNLESS(KThread::InitializeKernelThread(new_thread, ThreadFunction, reinterpret_cast<uintptr_t>(this), ThreadPriority, core_id));
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/* Register the new thread. */
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KThread::Register(new_thread);
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/* Run the thread. */
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MESOSPHERE_R_ABORT_UNLESS(new_thread->Run());
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}
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virtual KInterruptTask *OnInterrupt(s32 interrupt_id) override {
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MESOSPHERE_UNUSED(interrupt_id);
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this->ProcessOperation();
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m_target_cores &= ~(1ul << GetCurrentCoreId());
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return nullptr;
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}
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void RequestOperation(Operation op) {
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KScopedLightLock lk(m_lock);
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/* Create core masks for us to use. */
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constexpr u64 AllCoresMask = (1ul << cpu::NumCores) - 1ul;
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const u64 other_cores_mask = AllCoresMask & ~(1ul << GetCurrentCoreId());
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if ((op == Operation::InstructionMemoryBarrier) || (Kernel::GetState() == Kernel::State::Initializing)) {
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/* Check that there's no on-going operation. */
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MESOSPHERE_ABORT_UNLESS(m_operation == Operation::Idle);
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MESOSPHERE_ABORT_UNLESS(m_target_cores.Load() == 0);
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/* Set operation. */
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m_operation = op;
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/* For certain operations, we want to send an interrupt. */
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m_target_cores = other_cores_mask;
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const u64 target_mask = m_target_cores.Load();
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DataSynchronizationBarrierInnerShareable();
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Kernel::GetInterruptManager().SendInterProcessorInterrupt(KInterruptName_CacheOperation, target_mask);
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this->ProcessOperation();
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while (m_target_cores.Load() != 0) {
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cpu::Yield();
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}
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/* Go idle again. */
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m_operation = Operation::Idle;
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} else {
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/* Lock condvar so that we can send and wait for acknowledgement of request. */
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KScopedLightLock cv_lk(m_cv_lock);
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/* Check that there's no on-going operation. */
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MESOSPHERE_ABORT_UNLESS(m_operation == Operation::Idle);
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MESOSPHERE_ABORT_UNLESS(m_target_cores.Load() == 0);
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/* Set operation. */
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m_operation = op;
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/* Request all cores. */
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m_target_cores = AllCoresMask;
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/* Use the condvar. */
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m_cv.Broadcast();
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while (m_target_cores.Load() != 0) {
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m_cv.Wait(std::addressof(m_cv_lock));
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}
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/* Go idle again. */
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m_operation = Operation::Idle;
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}
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}
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};
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/* Instances of the interrupt handlers. */
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constinit KThreadTerminationInterruptHandler g_thread_termination_handler;
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constinit KCacheHelperInterruptHandler g_cache_operation_handler;
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constinit KCoreBarrierInterruptHandler g_core_barrier_handler;
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#if defined(MESOSPHERE_ENABLE_PERFORMANCE_COUNTER)
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constinit KPerformanceCounterInterruptHandler g_performance_counter_handler[cpu::NumCores];
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#endif
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/* Expose this as a global, for asm to use. */
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constinit s32 g_all_core_sync_count;
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template<typename F>
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ALWAYS_INLINE void PerformCacheOperationBySetWayImpl(int level, F f) {
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/* Used in multiple locations. */
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const u64 level_sel_value = static_cast<u64>(level << 1);
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/* Get the cache size id register value with interrupts disabled. */
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u64 ccsidr_value;
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{
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/* Disable interrupts. */
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KScopedInterruptDisable di;
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/* Configure the cache select register for our level. */
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cpu::SetCsselrEl1(level_sel_value);
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/* Ensure our configuration takes before reading the cache size id register. */
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cpu::InstructionMemoryBarrier();
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/* Get the cache size id register. */
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ccsidr_value = cpu::GetCcsidrEl1();
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}
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/* Ensure that no memory inconsistencies occur between cache management invocations. */
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cpu::DataSynchronizationBarrier();
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/* Get cache size id info. */
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CacheSizeIdRegisterAccessor ccsidr_el1(ccsidr_value);
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const int num_sets = ccsidr_el1.GetNumberOfSets();
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const int num_ways = ccsidr_el1.GetAssociativity();
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const int line_size = ccsidr_el1.GetLineSize();
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const u64 way_shift = static_cast<u64>(__builtin_clz(num_ways));
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const u64 set_shift = static_cast<u64>(line_size + 4);
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for (int way = 0; way <= num_ways; way++) {
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for (int set = 0; set <= num_sets; set++) {
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const u64 way_value = static_cast<u64>(way) << way_shift;
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const u64 set_value = static_cast<u64>(set) << set_shift;
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f(way_value | set_value | level_sel_value);
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}
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}
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}
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ALWAYS_INLINE void FlushDataCacheLineBySetWayImpl(const u64 sw_value) {
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__asm__ __volatile__("dc cisw, %[v]" :: [v]"r"(sw_value) : "memory");
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}
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ALWAYS_INLINE void StoreDataCacheLineBySetWayImpl(const u64 sw_value) {
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__asm__ __volatile__("dc csw, %[v]" :: [v]"r"(sw_value) : "memory");
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}
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void StoreDataCacheBySetWay(int level) {
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PerformCacheOperationBySetWayImpl(level, StoreDataCacheLineBySetWayImpl);
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}
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void FlushDataCacheBySetWay(int level) {
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PerformCacheOperationBySetWayImpl(level, FlushDataCacheLineBySetWayImpl);
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}
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void KCacheHelperInterruptHandler::ProcessOperation() {
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switch (m_operation) {
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case Operation::Idle:
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break;
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case Operation::InstructionMemoryBarrier:
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InstructionMemoryBarrier();
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break;
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case Operation::StoreDataCache:
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StoreDataCacheBySetWay(0);
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cpu::DataSynchronizationBarrier();
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break;
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case Operation::FlushDataCache:
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FlushDataCacheBySetWay(0);
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cpu::DataSynchronizationBarrier();
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break;
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}
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}
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ALWAYS_INLINE Result InvalidateDataCacheRange(uintptr_t start, uintptr_t end) {
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MESOSPHERE_ASSERT(util::IsAligned(start, DataCacheLineSize));
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MESOSPHERE_ASSERT(util::IsAligned(end, DataCacheLineSize));
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R_UNLESS(UserspaceAccess::InvalidateDataCache(start, end), svc::ResultInvalidCurrentMemory());
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DataSynchronizationBarrier();
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R_SUCCEED();
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}
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ALWAYS_INLINE Result StoreDataCacheRange(uintptr_t start, uintptr_t end) {
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MESOSPHERE_ASSERT(util::IsAligned(start, DataCacheLineSize));
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MESOSPHERE_ASSERT(util::IsAligned(end, DataCacheLineSize));
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R_UNLESS(UserspaceAccess::StoreDataCache(start, end), svc::ResultInvalidCurrentMemory());
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DataSynchronizationBarrier();
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R_SUCCEED();
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}
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ALWAYS_INLINE Result FlushDataCacheRange(uintptr_t start, uintptr_t end) {
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MESOSPHERE_ASSERT(util::IsAligned(start, DataCacheLineSize));
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MESOSPHERE_ASSERT(util::IsAligned(end, DataCacheLineSize));
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R_UNLESS(UserspaceAccess::FlushDataCache(start, end), svc::ResultInvalidCurrentMemory());
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DataSynchronizationBarrier();
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R_SUCCEED();
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}
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ALWAYS_INLINE void InvalidateEntireInstructionCacheLocalImpl() {
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__asm__ __volatile__("ic iallu" ::: "memory");
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}
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ALWAYS_INLINE void InvalidateEntireInstructionCacheGlobalImpl() {
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__asm__ __volatile__("ic ialluis" ::: "memory");
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}
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}
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void SynchronizeCores(u64 core_mask) {
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/* Request a core barrier interrupt. */
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g_core_barrier_handler.SynchronizeCores(core_mask);
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}
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void StoreCacheForInit(void *addr, size_t size) {
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/* Store the data cache for the specified range. */
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const uintptr_t start = util::AlignDown(reinterpret_cast<uintptr_t>(addr), DataCacheLineSize);
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const uintptr_t end = start + size;
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for (uintptr_t cur = start; cur < end; cur += DataCacheLineSize) {
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__asm__ __volatile__("dc cvac, %[cur]" :: [cur]"r"(cur) : "memory");
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}
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/* Data synchronization barrier. */
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DataSynchronizationBarrierInnerShareable();
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/* Invalidate instruction cache. */
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InvalidateEntireInstructionCacheLocalImpl();
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/* Ensure local instruction consistency. */
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EnsureInstructionConsistency();
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}
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void FlushEntireDataCache() {
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KScopedCoreMigrationDisable dm;
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CacheLineIdRegisterAccessor clidr_el1;
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const int levels_of_coherency = clidr_el1.GetLevelsOfCoherency();
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/* Store cache from L2 up to the level of coherence (if there's an L3 cache or greater). */
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for (int level = 2; level < levels_of_coherency; ++level) {
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StoreDataCacheBySetWay(level - 1);
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}
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/* Flush cache from the level of coherence down to L2. */
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for (int level = levels_of_coherency; level > 1; --level) {
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FlushDataCacheBySetWay(level - 1);
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}
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/* Data synchronization barrier for full system. */
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DataSynchronizationBarrier();
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}
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Result InvalidateDataCache(void *addr, size_t size) {
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/* Mark ourselves as in a cache maintenance operation, and prevent re-ordering. */
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KScopedCacheMaintenance cm;
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const uintptr_t start = reinterpret_cast<uintptr_t>(addr);
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const uintptr_t end = start + size;
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uintptr_t aligned_start = util::AlignDown(start, DataCacheLineSize);
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uintptr_t aligned_end = util::AlignUp(end, DataCacheLineSize);
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if (aligned_start != start) {
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R_TRY(FlushDataCacheRange(aligned_start, aligned_start + DataCacheLineSize));
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aligned_start += DataCacheLineSize;
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}
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if (aligned_start < aligned_end && (aligned_end != end)) {
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aligned_end -= DataCacheLineSize;
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R_TRY(FlushDataCacheRange(aligned_end, aligned_end + DataCacheLineSize));
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}
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if (aligned_start < aligned_end) {
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R_TRY(InvalidateDataCacheRange(aligned_start, aligned_end));
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}
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R_SUCCEED();
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}
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Result StoreDataCache(const void *addr, size_t size) {
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/* Mark ourselves as in a cache maintenance operation, and prevent re-ordering. */
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KScopedCacheMaintenance cm;
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const uintptr_t start = util::AlignDown(reinterpret_cast<uintptr_t>(addr), DataCacheLineSize);
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const uintptr_t end = util::AlignUp( reinterpret_cast<uintptr_t>(addr) + size, DataCacheLineSize);
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R_RETURN(StoreDataCacheRange(start, end));
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}
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Result FlushDataCache(const void *addr, size_t size) {
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/* Mark ourselves as in a cache maintenance operation, and prevent re-ordering. */
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KScopedCacheMaintenance cm;
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const uintptr_t start = util::AlignDown(reinterpret_cast<uintptr_t>(addr), DataCacheLineSize);
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const uintptr_t end = util::AlignUp( reinterpret_cast<uintptr_t>(addr) + size, DataCacheLineSize);
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|
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R_RETURN(FlushDataCacheRange(start, end));
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}
|
|
|
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void InvalidateEntireInstructionCache() {
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KScopedCoreMigrationDisable dm;
|
|
|
|
/* Invalidate the instruction cache on all cores. */
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|
InvalidateEntireInstructionCacheGlobalImpl();
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|
EnsureInstructionConsistency();
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|
|
|
/* Request the interrupt helper to perform an instruction memory barrier. */
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|
g_cache_operation_handler.RequestOperation(KCacheHelperInterruptHandler::Operation::InstructionMemoryBarrier);
|
|
}
|
|
|
|
void InitializeInterruptThreads(s32 core_id) {
|
|
/* Initialize the cache operation handler. */
|
|
g_cache_operation_handler.Initialize(core_id);
|
|
|
|
/* Bind all handlers to the relevant interrupts. */
|
|
MESOSPHERE_R_ABORT_UNLESS(Kernel::GetInterruptManager().BindHandler(std::addressof(g_cache_operation_handler), KInterruptName_CacheOperation, core_id, KInterruptController::PriorityLevel_High, false, false));
|
|
MESOSPHERE_R_ABORT_UNLESS(Kernel::GetInterruptManager().BindHandler(std::addressof(g_thread_termination_handler), KInterruptName_ThreadTerminate, core_id, KInterruptController::PriorityLevel_Scheduler, false, false));
|
|
MESOSPHERE_R_ABORT_UNLESS(Kernel::GetInterruptManager().BindHandler(std::addressof(g_core_barrier_handler), KInterruptName_CoreBarrier, core_id, KInterruptController::PriorityLevel_Scheduler, false, false));
|
|
|
|
/* If we should, enable user access to the performance counter registers. */
|
|
if (KTargetSystem::IsUserPmuAccessEnabled()) { SetPmUserEnrEl0(1ul); }
|
|
|
|
/* If we should, enable the kernel performance counter interrupt handler. */
|
|
#if defined(MESOSPHERE_ENABLE_PERFORMANCE_COUNTER)
|
|
MESOSPHERE_R_ABORT_UNLESS(Kernel::GetInterruptManager().BindHandler(std::addressof(g_performance_counter_handler[core_id]), KInterruptName_PerformanceCounter, core_id, KInterruptController::PriorityLevel_Timer, false, false));
|
|
#endif
|
|
}
|
|
|
|
void SynchronizeAllCores() {
|
|
SynchronizeAllCoresImpl(&g_all_core_sync_count, static_cast<s32>(cpu::NumCores));
|
|
}
|
|
|
|
}
|