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remove C0Tcr6Ma aaaaaaaa VVVVVVVV (VVVVVVVV)

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This commit is contained in:
tomvita 2025-01-08 13:16:51 +08:00
parent 38ed75cc00
commit 52d2df33c7
3 changed files with 0 additions and 21 deletions
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2
docs/features/cheats.md
View File

@ -328,7 +328,6 @@ C0TcS2Ra aaaaaaaa
C0TcS3Rr C0TcS3Rr
C0TcS400 VVVVVVVV (VVVVVVVV) C0TcS400 VVVVVVVV (VVVVVVVV)
C0TcS5X0 C0TcS5X0
C0Tcr6Ma aaaaaaaa VVVVVVVV (VVVVVVVV)
``` ```
+ T: Width of memory write (1, 2, 4, or 8 bytes). + T: Width of memory write (1, 2, 4, or 8 bytes).
@ -349,7 +348,6 @@ C0Tcr6Ma aaaaaaaa VVVVVVVV (VVVVVVVV)
+ 3: Register + Offset Register + 3: Register + Offset Register
+ 4: Static Value + 4: Static Value
+ 5: Other Register + 5: Other Register
+ 6: Compare [Memory Base + Offset Register + Relative Offset] against Static Value
#### Conditions #### Conditions
+ 1: > + 1: >

18
stratosphere/dmnt/source/cheat/impl/dmnt_cheat_vm.cpp
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@ -235,13 +235,6 @@ namespace ams::dmnt::cheat::impl {
this->LogToDebugFile("A Reg Idx: %x\n", opcode->begin_reg_cond.addr_reg_index); this->LogToDebugFile("A Reg Idx: %x\n", opcode->begin_reg_cond.addr_reg_index);
this->LogToDebugFile("O Reg Idx: %x\n", opcode->begin_reg_cond.ofs_reg_index); this->LogToDebugFile("O Reg Idx: %x\n", opcode->begin_reg_cond.ofs_reg_index);
break; break;
case CompareRegisterValueType_OffsetValue:
this->LogToDebugFile("Comp Type: Offset Value\n");
this->LogToDebugFile("Mem Type: %x\n", opcode->begin_reg_cond.mem_type);
this->LogToDebugFile("O Reg Idx: %x\n", opcode->begin_reg_cond.ofs_reg_index);
this->LogToDebugFile("Rel Addr: %lx\n", opcode->begin_reg_cond.rel_address);
this->LogToDebugFile("Value: %lx\n", opcode->begin_reg_cond.value.bit64);
break;
} }
break; break;
case CheatVmOpcodeType_SaveRestoreRegister: case CheatVmOpcodeType_SaveRestoreRegister:
@ -551,7 +544,6 @@ namespace ams::dmnt::cheat::impl {
/* C0TcS3Rr */ /* C0TcS3Rr */
/* C0TcS400 VVVVVVVV (VVVVVVVV) */ /* C0TcS400 VVVVVVVV (VVVVVVVV) */
/* C0TcS5X0 */ /* C0TcS5X0 */
/* C0Tcr6Ma aaaaaaaa VVVVVVVV (VVVVVVVV) */
/* C0 = opcode 0xC0 */ /* C0 = opcode 0xC0 */
/* T = bit width */ /* T = bit width */
/* c = condition type. */ /* c = condition type. */
@ -592,12 +584,6 @@ namespace ams::dmnt::cheat::impl {
opcode.begin_reg_cond.addr_reg_index = ((first_dword >> 4) & 0xF); opcode.begin_reg_cond.addr_reg_index = ((first_dword >> 4) & 0xF);
opcode.begin_reg_cond.ofs_reg_index = (first_dword & 0xF); opcode.begin_reg_cond.ofs_reg_index = (first_dword & 0xF);
break; break;
case CompareRegisterValueType_OffsetValue:
opcode.begin_reg_cond.mem_type = (MemoryAccessType)((first_dword >> 4) & 0xF);
opcode.begin_reg_cond.rel_address = (((u64)(first_dword & 0xF) << 32ul) | ((u64)GetNextDword()));
opcode.begin_reg_cond.ofs_reg_index = ((first_dword >> 12) & 0xF);
opcode.begin_reg_cond.value = GetNextVmInt(opcode.begin_reg_cond.bit_width);
break;
} }
} }
break; break;
@ -1208,10 +1194,6 @@ namespace ams::dmnt::cheat::impl {
case CompareRegisterValueType_RegisterOfsReg: case CompareRegisterValueType_RegisterOfsReg:
cond_address = m_registers[cur_opcode.begin_reg_cond.addr_reg_index] + m_registers[cur_opcode.begin_reg_cond.ofs_reg_index]; cond_address = m_registers[cur_opcode.begin_reg_cond.addr_reg_index] + m_registers[cur_opcode.begin_reg_cond.ofs_reg_index];
break; break;
case CompareRegisterValueType_OffsetValue:
cond_address = GetCheatProcessAddress(metadata, cur_opcode.begin_reg_cond.mem_type, cur_opcode.begin_reg_cond.rel_address + m_registers[cur_opcode.begin_reg_cond.ofs_reg_index]);
src_value = GetVmInt(cur_opcode.begin_reg_cond.value, cur_opcode.begin_reg_cond.bit_width);
break;
default: default:
break; break;
} }

1
stratosphere/dmnt/source/cheat/impl/dmnt_cheat_vm.hpp
View File

@ -108,7 +108,6 @@ namespace ams::dmnt::cheat::impl {
CompareRegisterValueType_RegisterOfsReg = 3, CompareRegisterValueType_RegisterOfsReg = 3,
CompareRegisterValueType_StaticValue = 4, CompareRegisterValueType_StaticValue = 4,
CompareRegisterValueType_OtherRegister = 5, CompareRegisterValueType_OtherRegister = 5,
CompareRegisterValueType_OffsetValue = 6,
}; };
enum SaveRestoreRegisterOpType : u32 { enum SaveRestoreRegisterOpType : u32 {