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Add type 1 extension
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@ -62,11 +62,13 @@ Code type 0x1 performs a comparison of the contents of memory to a static value.
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If the condition is not met, all instructions until the appropriate End or Else conditional block terminator are skipped.
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If the condition is not met, all instructions until the appropriate End or Else conditional block terminator are skipped.
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#### Encoding
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#### Encoding
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`1TMC00AA AAAAAAAA VVVVVVVV (VVVVVVVV)`
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`1TMCXrAA AAAAAAAA VVVVVVVV (VVVVVVVV)`
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+ T: Width of memory write (1, 2, 4, or 8 bytes).
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+ T: Width of memory read (1, 2, 4, or 8 bytes).
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+ M: Memory region to write to (0 = Main NSO, 1 = Heap, 2 = Alias, 3 = Aslr).
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+ M: Memory region to read from (0 = Main NSO, 1 = Heap, 2 = Alias, 3 = Aslr, 4 = none).
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+ C: Condition to use, see below.
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+ C: Condition to use, see below.
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+ X: Operand Type, see below.
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+ r: Offset Register (operand types 1).
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+ A: Immediate offset to use from memory region base.
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+ A: Immediate offset to use from memory region base.
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+ V: Value to compare to.
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+ V: Value to compare to.
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@ -78,6 +80,9 @@ If the condition is not met, all instructions until the appropriate End or Else
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+ 5: ==
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+ 5: ==
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+ 6: !=
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+ 6: !=
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#### Operand Type
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+ 0: Memory Base + Relative Offset
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+ 1: Memory Base + Offset Register + Relative Offset
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---
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---
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### Code Type 0x2: End Conditional Block
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### Code Type 0x2: End Conditional Block
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@ -126,7 +131,7 @@ Code type 0x5 allows loading a value from memory into a register, either using a
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`5TMR00AA AAAAAAAA`
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`5TMR00AA AAAAAAAA`
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+ T: Width of memory read (1, 2, 4, or 8 bytes).
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+ T: Width of memory read (1, 2, 4, or 8 bytes).
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+ M: Memory region to write to (0 = Main NSO, 1 = Heap, 2 = Alias, 3 = Aslr).
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+ M: Memory region to write to (0 = Main NSO, 1 = Heap, 2 = Alias, 3 = Aslr, 4 = none).
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+ R: Register to load value into.
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+ R: Register to load value into.
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+ A: Immediate offset to use from memory region base.
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+ A: Immediate offset to use from memory region base.
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@ -149,7 +154,7 @@ Code type 0x5 allows loading a value from memory into a register, either using a
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`5TMR3SAA AAAAAAAA`
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`5TMR3SAA AAAAAAAA`
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+ T: Width of memory read (1, 2, 4, or 8 bytes).
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+ T: Width of memory read (1, 2, 4, or 8 bytes).
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+ M: Memory region to write to (0 = Main NSO, 1 = Heap, 2 = Alias, 3 = Aslr).
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+ M: Memory region to write to (0 = Main NSO, 1 = Heap, 2 = Alias, 3 = Aslr, 4 = none).
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+ R: Register to load value into.
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+ R: Register to load value into.
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+ S: Register to use as offset register.
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+ S: Register to use as offset register.
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+ A: Immediate offset to use from memory region base.
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+ A: Immediate offset to use from memory region base.
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@ -108,6 +108,8 @@ namespace ams::dmnt::cheat::impl {
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this->LogToDebugFile("Bit Width: %x\n", opcode->begin_cond.bit_width);
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this->LogToDebugFile("Bit Width: %x\n", opcode->begin_cond.bit_width);
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this->LogToDebugFile("Mem Type: %x\n", opcode->begin_cond.mem_type);
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this->LogToDebugFile("Mem Type: %x\n", opcode->begin_cond.mem_type);
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this->LogToDebugFile("Cond Type: %x\n", opcode->begin_cond.cond_type);
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this->LogToDebugFile("Cond Type: %x\n", opcode->begin_cond.cond_type);
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this->LogToDebugFile("Inc Ofs reg: %d\n", opcode->begin_cond.include_ofs_reg);
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this->LogToDebugFile("Ofs Reg Idx: %x\n", opcode->begin_cond.ofs_reg_index);
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this->LogToDebugFile("Rel Addr: %lx\n", opcode->begin_cond.rel_address);
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this->LogToDebugFile("Rel Addr: %lx\n", opcode->begin_cond.rel_address);
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this->LogToDebugFile("Value: %lx\n", opcode->begin_cond.value.bit64);
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this->LogToDebugFile("Value: %lx\n", opcode->begin_cond.value.bit64);
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break;
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break;
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@ -400,6 +402,8 @@ namespace ams::dmnt::cheat::impl {
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opcode.begin_cond.bit_width = (first_dword >> 24) & 0xF;
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opcode.begin_cond.bit_width = (first_dword >> 24) & 0xF;
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opcode.begin_cond.mem_type = (MemoryAccessType)((first_dword >> 20) & 0xF);
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opcode.begin_cond.mem_type = (MemoryAccessType)((first_dword >> 20) & 0xF);
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opcode.begin_cond.cond_type = (ConditionalComparisonType)((first_dword >> 16) & 0xF);
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opcode.begin_cond.cond_type = (ConditionalComparisonType)((first_dword >> 16) & 0xF);
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opcode.begin_cond.include_ofs_reg = ((first_dword >> 12) & 0xF) != 0;
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opcode.begin_cond.ofs_reg_index = ((first_dword >> 8) & 0xF);
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opcode.begin_cond.rel_address = ((u64)(first_dword & 0xFF) << 32ul) | ((u64)second_dword);
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opcode.begin_cond.rel_address = ((u64)(first_dword & 0xFF) << 32ul) | ((u64)second_dword);
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opcode.begin_cond.value = GetNextVmInt(opcode.begin_cond.bit_width);
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opcode.begin_cond.value = GetNextVmInt(opcode.begin_cond.bit_width);
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}
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}
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@ -856,7 +860,7 @@ namespace ams::dmnt::cheat::impl {
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case CheatVmOpcodeType_BeginConditionalBlock:
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case CheatVmOpcodeType_BeginConditionalBlock:
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{
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{
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/* Read value from memory. */
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/* Read value from memory. */
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u64 src_address = GetCheatProcessAddress(metadata, cur_opcode.begin_cond.mem_type, cur_opcode.begin_cond.rel_address);
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u64 src_address = GetCheatProcessAddress(metadata, cur_opcode.begin_cond.mem_type, (cur_opcode.begin_cond.include_ofs_reg) ? m_registers[cur_opcode.begin_cond.ofs_reg_index] + cur_opcode.begin_cond.rel_address : cur_opcode.begin_cond.rel_address);
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u64 src_value = 0;
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u64 src_value = 0;
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switch (cur_opcode.store_static.bit_width) {
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switch (cur_opcode.store_static.bit_width) {
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case 1:
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case 1:
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@ -145,6 +145,8 @@ namespace ams::dmnt::cheat::impl {
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u32 bit_width;
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u32 bit_width;
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MemoryAccessType mem_type;
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MemoryAccessType mem_type;
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ConditionalComparisonType cond_type;
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ConditionalComparisonType cond_type;
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bool include_ofs_reg;
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u32 ofs_reg_index;
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u64 rel_address;
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u64 rel_address;
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VmInt value;
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VmInt value;
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};
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};
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