diff --git a/exosphere/src/bootup.c b/exosphere/src/bootup.c
index de5e7a1b5..cb19a6b90 100644
--- a/exosphere/src/bootup.c
+++ b/exosphere/src/bootup.c
@@ -66,28 +66,29 @@ void bootup_misc_mmio(void) {
     APBDEV_PMC_DPD_ENABLE_0 = 0;
 
     /* Setup MC. */
-    MAKE_MC_REG(MC_REGISTER_VIDEO_PROTECT_GPU_OVERRIDE_0_0) = 1;
+    volatile mc_register_t *mc_register = get_mc_reg();
+    mc_register->VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 1;
 
     /* undefined in reference manual */
-    MAKE_MC_REG(MC_REGISTER_0x648) = 0;
-    MAKE_MC_REG(MC_REGISTER_0x64C) = 0;
-    MAKE_MC_REG(MC_REGISTER_0x650) = 1;
+    mc_register->_0x648 = 0;
+    mc_register->_0x64C = 0;
+    mc_register->_0x650 = 1;
 
     /* disable SEC carveout */
-    MAKE_MC_REG(MC_REGISTER_SEC_CARVEOUT_BOM_0) = 0;
-    MAKE_MC_REG(MC_REGISTER_SEC_CARVEOUT_SIZE_MB_0) = 0; 
-    MAKE_MC_REG(MC_REGISTER_SEC_CARVEOUT_REG_CTRL_0) = 1;
+    mc_register->SEC_CARVEOUT_BOM_0 = 0;
+    mc_register->SEC_CARVEOUT_SIZE_MB_0 = 0;
+    mc_register->SEC_CARVEOUT_REG_CTRL_0 = 1;
 
     /* disable MTS carveout */
-    MAKE_MC_REG(MC_REGISTER_MTS_CARVEOUT_BOM_0) = 0;
-    MAKE_MC_REG(MC_REGISTER_MTS_CARVEOUT_SIZE_MB_0) = 0;
-    MAKE_MC_REG(MC_REGISTER_MTS_CARVEOUT_ADR_HI_0) = 0;
-    MAKE_MC_REG(MC_REGISTER_MTS_CARVEOUT_REG_CTRL_0) = 1;
+    mc_register->MTS_CARVEOUT_BOM_0 = 0;
+    mc_register->MTS_CARVEOUT_SIZE_MB_0 = 0;
+    mc_register->MTS_CARVEOUT_ADR_HI_0 = 0;
+    mc_register->MTS_CARVEOUT_REG_CTRL_0 = 1;
 
     /* disable security carveout - SECURITY_CFG0_0, CFG1_0, CFG3_0 */
-    MAKE_MC_REG(MC_REGISTER_SECURITY_BOM) = 0;
-    MAKE_MC_REG(MC_REGISTER_SECURITY_SIZE_MB) = 0;
-    MAKE_MC_REG(MC_REGISTER_SECURITY_BOM_HI) = 0x11;
+    mc_register->SECURITY_BOM = 0;
+    mc_register->SECURITY_SIZE_MB = 0;
+    mc_register->SECURITY_BOM_HI = 0x11;
 
     configure_default_carveouts();
 
@@ -115,40 +116,42 @@ void bootup_misc_mmio(void) {
     APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 = sec_disable_2;
 
     /* reset translation tables to allow all */
-    MAKE_MC_REG(MC_REGISTER_SMMU_TRANSLATION_ENABLE_0_0) = 0xFFFFFFFF;
-    MAKE_MC_REG(MC_REGISTER_SMMU_TRANSLATION_ENABLE_1_0) = 0xFFFFFFFF;
-    MAKE_MC_REG(MC_REGISTER_SMMU_TRANSLATION_ENABLE_2_0) = 0xFFFFFFFF;
-    MAKE_MC_REG(MC_REGISTER_SMMU_TRANSLATION_ENABLE_3_0) = 0xFFFFFFFF;
-    MAKE_MC_REG(MC_REGISTER_SMMU_TRANSLATION_ENABLE_4_0) = 0xFFFFFFFF;
+    mc_register->SMMU_TRANSLATION_ENABLE_0_0 = 0xFFFFFFFF;
+    mc_register->SMMU_TRANSLATION_ENABLE_1_0 = 0xFFFFFFFF;
+    mc_register->SMMU_TRANSLATION_ENABLE_2_0 = 0xFFFFFFFF;
+    mc_register->SMMU_TRANSLATION_ENABLE_3_0 = 0xFFFFFFFF;
+    mc_register->SMMU_TRANSLATION_ENABLE_4_0 = 0xFFFFFFFF;
 
-    MAKE_MC_REG(MC_REGISTER_0x38) = 0;
-    MAKE_MC_REG(MC_REGISTER_0x3C) = 0;
+    /* unknown null */
+    mc_register->_0x38 = 0;
+    mc_register->_0x3C = 0;
 
     /* disable stall calls after ring1 and ring3 requests */
-    MAKE_MC_REG(MC_REGISTER_EMEM_ARB_RING1_THROTTLE_0) = 0;
-    MAKE_MC_REG(MC_REGISTER_EMEM_ARB_RING3_THROTTLE_0) = 0;
+    mc_register->EMEM_ARB_RING1_THROTTLE_0 = 0;
+    mc_register->EMEM_ARB_RING3_THROTTLE_0 = 0;
 
-    MAKE_MC_REG(MC_REGISTER_EMEM_ARB_OVERRIDE_0) = 0; /* disable overrides */
-    MAKE_MC_REG(MC_REGISTER_EMEM_ARB_RSV_0) = 0; /*  null reserved register */
+    mc_register->EMEM_ARB_OVERRIDE_0 = 0; /* disable overrides */
+    mc_register->EMEM_ARB_RSV_0 = 0; /*  null reserved register */
 
-    MAKE_MC_REG(MC_REGISTER_0xF0) = 0;
+    /* unknown null */
+    mc_register->_0xF0 = 0;
 
     /* disable clock-enable overrides */
-    MAKE_MC_REG(MC_REGISTER_CLKEN_OVERRIDE_0) = 0;
-    
+    mc_register->CLKEN_OVERRIDE_0 = 0;
+
     /* reset PTB, TLB and PTC */
-    MAKE_MC_REG(MC_REGISTER_SMMU_PTB_DATA_0) = 0;
-    MAKE_MC_REG(MC_REGISTER_SMMU_TLB_CONFIG_0) = 0x30000030;
-    MAKE_MC_REG(MC_REGISTER_SMMU_PTC_CONFIG_0) = 0x2800003F;
+    mc_register->SMMU_PTB_DATA_0 = 0;
+    mc_register->SMMU_TLB_CONFIG_0 = 0x30000030;
+    mc_register->SMMU_PTC_CONFIG_0 = 0x2800003F;
 
     /* TODO: What are these MC reg writes? */
-    (void)(MAKE_MC_REG(MC_REGISTER_SMMU_TLB_CONFIG_0));
-    MAKE_MC_REG(MC_REGISTER_SMMU_PTC_FLUSH_0) = 0;
-    (void)(MAKE_MC_REG(MC_REGISTER_SMMU_TLB_CONFIG_0));
-    MAKE_MC_REG(MC_REGISTER_SMMU_TLB_FLUSH_0) = 0;
-    (void)(MAKE_MC_REG(MC_REGISTER_SMMU_TLB_CONFIG_0));
-    MAKE_MC_REG(MC_REGISTER_SMMU_CONFIG_0) = 0x1; /* enable SMMU */
-    (void)(MAKE_MC_REG(MC_REGISTER_SMMU_TLB_CONFIG_0));
+    (void)(mc_register->SMMU_TLB_CONFIG_0);
+    mc_register->SMMU_PTC_FLUSH_0 = 0;
+    (void)(mc_register->SMMU_TLB_CONFIG_0);
+    mc_register->SMMU_TLB_FLUSH_0 = 0;
+    (void)(mc_register->SMMU_TLB_CONFIG_0);
+    mc_register->SMMU_CONFIG_0 = 0x1; /* enable SMMU */
+    (void)(mc_register->SMMU_TLB_CONFIG_0);
 
     /* Clear RESET Vector, setup CPU Secure Boot RESET Vectors. */
     uint32_t reset_vec = TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_WARMBOOT_CRT0_AND_MAIN);
@@ -188,18 +191,19 @@ void bootup_misc_mmio(void) {
         g_has_booted_up = true;
     } else if (exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_400) {
         /* TODO: What are these MC reg writes? */
-        MAKE_MC_REG(MC_REGISTER_0x65C) = 0xFFFFF000;
-        MAKE_MC_REG(MC_REGISTER_0x660) = 0;
-        MAKE_MC_REG(MC_REGISTER_IRAM_REG_CTRL_0) |= 1; /* overlap at 18.11.1.86 and 18.11.1.87 - lock write access to IRAM and EMEM registers */
+        mc_register->_0x65C = 0xFFFFF000;
+        mc_register->_0x660 = 0;
+        mc_register->EMEM_CFG_ACCESS_CTRL_0_AND_IRAM_REG_CTRL_0 |= 1; /* overlap at 18.11.1.86 and 18.11.1.87 - lock write access to IRAM and EMEM registers */
         CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0 &= 0xFFF7FFFF;
     }
 }
 
 void setup_4x_mmio(void) {
+    volatile mc_register_t *mc_register = get_mc_reg();
     /* TODO: What are these MC reg writes? */
-    MAKE_MC_REG(MC_REGISTER_0x65C) = 0xFFFFF000;
-    MAKE_MC_REG(MC_REGISTER_0x660) = 0;
-    MAKE_MC_REG(MC_REGISTER_IRAM_REG_CTRL_0) |= 1; /* as above, lock write access to IRAM and EMEM registers */
+    mc_register->_0x65C = 0xFFFFF000;
+    mc_register->_0x660 = 0;
+    mc_register->EMEM_CFG_ACCESS_CTRL_0_AND_IRAM_REG_CTRL_0 |= 1; /* as above, lock write access to IRAM and EMEM registers */
     CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0 &= 0xFFF7FFFF;
 
     /* TODO: What are these PMC scratch writes? */
@@ -218,6 +222,7 @@ void setup_4x_mmio(void) {
     APBDEV_PMC_SECURE_SCRATCH103_0 = 0x0;
     APBDEV_PMC_SECURE_SCRATCH39_0 = (APBDEV_PMC_SECURE_SCRATCH39_0 & 0xF8000000) | 0x88;
     /* TODO: Do we want to bother locking the secure scratch registers? */
+
     /* 4.x Jamais Vu mitigations. */
     /* Overwrite exception vectors. */
     BPMP_VECTOR_RESET = BPMP_MITIGATION_RESET_VAL;
@@ -228,8 +233,10 @@ void setup_4x_mmio(void) {
     BPMP_VECTOR_UNK = BPMP_MITIGATION_RESET_VAL;
     BPMP_VECTOR_IRQ = BPMP_MITIGATION_RESET_VAL;
     BPMP_VECTOR_FIQ = BPMP_MITIGATION_RESET_VAL;
+
     /* Disable AHB arbitration for the BPMP. */
     AHB_ARBITRATION_DISABLE_0 |= 2;
+
     /* Set SMMU for BPMP/APB-DMA to point to TZRAM. */
     MC_SMMU_PTB_ASID_0 = 1;
     MC_SMMU_PTB_DATA_0 = 0x70012;
@@ -239,6 +246,7 @@ void setup_4x_mmio(void) {
     while ((FLOW_CTLR_HALT_COP_EVENTS_0 >> 29) != 5) {
         wait(1);
     }
+
     /* If not in a debugging context, setup the activity monitor. */
     if ((get_debug_authentication_status() & 3) != 3) {
         FLOW_CTLR_HALT_COP_EVENTS_0 = 0x40000000;