From e9100b287dc8471b0091d348ff734048426cacb1 Mon Sep 17 00:00:00 2001 From: Michael Scire Date: Fri, 5 Jun 2020 04:07:56 -0700 Subject: [PATCH] exo2: add a number of minor configuration fixes --- .../include/exosphere/tegra/tegra_ahb_arbc.hpp | 12 ++++++++++++ .../include/exosphere/tegra/tegra_flow_ctlr.hpp | 2 +- libexosphere/source/gic/gic_api.cpp | 6 +++++- 3 files changed, 18 insertions(+), 2 deletions(-) diff --git a/libexosphere/include/exosphere/tegra/tegra_ahb_arbc.hpp b/libexosphere/include/exosphere/tegra/tegra_ahb_arbc.hpp index a131cf68..74bf76ee 100644 --- a/libexosphere/include/exosphere/tegra/tegra_ahb_arbc.hpp +++ b/libexosphere/include/exosphere/tegra/tegra_ahb_arbc.hpp @@ -24,3 +24,15 @@ #define AHB_MASTER_SWID_1 (0x038) #define AHB_GIZMO_TZRAM (0x054) +#define AHB_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (AHB_, NAME) +#define AHB_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (AHB_, NAME, VALUE) +#define AHB_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (AHB_, NAME, ENUM) +#define AHB_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(AHB_, NAME, __COND__, TRUE_ENUM, FALSE_ENUM) + +#define DEFINE_AHB_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (AHB_, NAME, __OFFSET__, __WIDTH__) +#define DEFINE_AHB_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (AHB_, NAME, __OFFSET__, ZERO, ONE) +#define DEFINE_AHB_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (AHB_, NAME, __OFFSET__, ZERO, ONE, TWO, THREE) +#define DEFINE_AHB_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(AHB_, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) +#define DEFINE_AHB_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (AHB_, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) + +DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_COP, 1, ENABLE, DISABLE); diff --git a/libexosphere/include/exosphere/tegra/tegra_flow_ctlr.hpp b/libexosphere/include/exosphere/tegra/tegra_flow_ctlr.hpp index 7c2f7891..d9077a9a 100644 --- a/libexosphere/include/exosphere/tegra/tegra_flow_ctlr.hpp +++ b/libexosphere/include/exosphere/tegra/tegra_flow_ctlr.hpp @@ -49,7 +49,7 @@ DEFINE_FLOW_REG_BIT_ENUM(CPUN_CSR_ENABLE, 0, DISABLE, ENABLE); DEFINE_FLOW_REG(CPUN_CSR_WAIT_WFI_BITMAP, 8, 4); -DEFINE_FLOW_REG_BIT_ENUM(CPUN_CSR_ENABLE_EXT, 12, DISABLE, ENABLE); +DEFINE_FLOW_REG_TWO_BIT_ENUM(CPUN_CSR_ENABLE_EXT, 12, POWERGATE_CPU_ONLY, POWERGATE_BOTH_CPU_NONCPU, POWERGATE_CPU_TURNOFF_CPURAIL, PG_EMULATION); DEFINE_FLOW_REG_BIT_ENUM(CPUN_CSR_EVENT_FLAG, 14, FALSE, TRUE); DEFINE_FLOW_REG_BIT_ENUM(CPUN_CSR_INTR_FLAG, 15, FALSE, TRUE); diff --git a/libexosphere/source/gic/gic_api.cpp b/libexosphere/source/gic/gic_api.cpp index 220713e7..f04b4656 100644 --- a/libexosphere/source/gic/gic_api.cpp +++ b/libexosphere/source/gic/gic_api.cpp @@ -124,7 +124,11 @@ namespace ams::gic { const int word = i / scale; const int bit = (i % scale) * width; - reg::ReadWrite(address + sizeof(u32) * word, REG_BITS_VALUE(bit, width, value)); + const u32 mask = ((1u << width) - 1) << bit; + + const uintptr_t reg_addr = address + sizeof(u32) * word; + const u32 old = reg::Read(reg_addr) & ~mask; + reg::Write(reg_addr, old | ((value << bit) & mask)); } void Write(uintptr_t address, int width, int i, u32 value) {