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https://github.com/Atmosphere-NX/Atmosphere-libs.git
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exo2: implement the first half of SmcCpuSuspend
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@ -27,6 +27,7 @@ namespace ams::clkrst {
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void EnableUartCClock();
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void EnableUartCClock();
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void EnableActmonClock();
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void EnableActmonClock();
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void EnableI2c1Clock();
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void EnableI2c1Clock();
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void EnableI2c5Clock();
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void DisableI2c1Clock();
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void DisableI2c1Clock();
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@ -25,5 +25,6 @@ namespace ams::flow {
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void SetCpuCsr(int core, u32 enable_ext);
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void SetCpuCsr(int core, u32 enable_ext);
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void SetHaltCpuEvents(int core, bool resume_on_irq);
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void SetHaltCpuEvents(int core, bool resume_on_irq);
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void SetCc4Ctrl(int core, u32 value);
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void SetCc4Ctrl(int core, u32 value);
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void ClearL2FlushControl();
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}
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}
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@ -36,6 +36,8 @@ namespace ams::pmc {
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void SetRegisterAddress(uintptr_t address);
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void SetRegisterAddress(uintptr_t address);
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void InitializeRandomScratch();
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void InitializeRandomScratch();
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void EnableWakeEventDetection();
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void ConfigureForSc7Entry();
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void LockSecureRegister(SecureRegister reg);
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void LockSecureRegister(SecureRegister reg);
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@ -29,5 +29,7 @@ namespace ams::pmic {
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void EnableVddCpu(Regulator regulator);
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void EnableVddCpu(Regulator regulator);
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void DisableVddCpu(Regulator regulator);
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void DisableVddCpu(Regulator regulator);
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void EnableSleep();
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bool IsAcOk();
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}
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}
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@ -18,6 +18,7 @@
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#define FLOW_CTLR_FLOW_DBG_QUAL (0x050)
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#define FLOW_CTLR_FLOW_DBG_QUAL (0x050)
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#define FLOW_CTLR_L2FLUSH_CONTROL (0x094)
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#define FLOW_CTLR_BPMP_CLUSTER_CONTROL (0x098)
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#define FLOW_CTLR_BPMP_CLUSTER_CONTROL (0x098)
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#define FLOW_CTLR_CPU0_CSR (0x008)
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#define FLOW_CTLR_CPU0_CSR (0x008)
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@ -212,3 +212,5 @@ DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_XUSBB, 21, DISABLE, ENABLE);
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DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_XUSBC, 22, DISABLE, ENABLE);
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DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_XUSBC, 22, DISABLE, ENABLE);
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DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_VIC, 23, DISABLE, ENABLE);
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DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_VIC, 23, DISABLE, ENABLE);
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DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_IRAM, 24, DISABLE, ENABLE);
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DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_IRAM, 24, DISABLE, ENABLE);
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DEFINE_PMC_REG_BIT_ENUM(CNTRL2_WAKE_DET_EN, 9, DISABLE, ENABLE);
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@ -105,7 +105,7 @@ namespace ams::clkrst {
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}
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}
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void EnableI2c5Clock() {
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void EnableI2c5Clock() {
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EnableClock(I2c1Clock);
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EnableClock(I2c5Clock);
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}
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}
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void DisableI2c1Clock() {
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void DisableI2c1Clock() {
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@ -76,4 +76,8 @@ namespace ams::flow {
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reg::Write(g_register_address + FlowControllerRegisterOffsets[core].cc4_core_ctrl, value);
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reg::Write(g_register_address + FlowControllerRegisterOffsets[core].cc4_core_ctrl, value);
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}
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}
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void ClearL2FlushControl() {
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reg::Write(g_register_address + FLOW_CTLR_L2FLUSH_CONTROL, 0);
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}
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}
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}
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@ -224,6 +224,32 @@ namespace ams::pmc {
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LockSecureRegister(SecureRegister_Srk);
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LockSecureRegister(SecureRegister_Srk);
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}
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}
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void EnableWakeEventDetection() {
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/* Get the address. */
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const uintptr_t address = g_register_address;
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/* Wait 75us, then enable event detection, then wait another 75us. */
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util::WaitMicroSeconds(75);
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reg::ReadWrite(address + APBDEV_PMC_CNTRL2, PMC_REG_BITS_ENUM(CNTRL2_WAKE_DET_EN, ENABLE));
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util::WaitMicroSeconds(75);
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/* Enable all wake events. */
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reg::Write(address + APBDEV_PMC_WAKE_STATUS, 0xFFFFFFFFu);
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reg::Write(address + APBDEV_PMC_WAKE2_STATUS, 0xFFFFFFFFu);
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util::WaitMicroSeconds(75);
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}
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void ConfigureForSc7Entry() {
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/* Get the address. */
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const uintptr_t address = g_register_address;
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/* Configure the bootrom to perform a warmboot. */
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reg::Write(address + APBDEV_PMC_SCRATCH0, 0x1);
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/* Enable the TSC multiplier. */
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reg::ReadWrite(address + APBDEV_PMC_DPD_ENABLE, PMC_REG_BITS_ENUM(DPD_ENABLE_TSC_MULT_EN, ENABLE));
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}
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void LockSecureRegister(SecureRegister reg) {
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void LockSecureRegister(SecureRegister reg) {
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/* Get the address. */
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/* Get the address. */
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const uintptr_t address = g_register_address;
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const uintptr_t address = g_register_address;
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@ -25,13 +25,17 @@ namespace ams::pmic {
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constexpr inline int I2cAddressMarikoMax77812_A = 0x31;
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constexpr inline int I2cAddressMarikoMax77812_A = 0x31;
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constexpr inline int I2cAddressMarikoMax77812_B = 0x33;
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constexpr inline int I2cAddressMarikoMax77812_B = 0x33;
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constexpr inline int I2cAddressMax77620Pmic = 0x3C;
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/* https://github.com/Atmosphere-NX/Atmosphere/blob/master/emummc/source/power/max77620.h */
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/* https://github.com/Atmosphere-NX/Atmosphere/blob/master/emummc/source/power/max7762x.h */
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/* https://github.com/Atmosphere-NX/Atmosphere/blob/master/emummc/source/power/max7762x.h */
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/* TODO: Find datasheet, link to it instead. */
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/* TODO: Find datasheet, link to it instead. */
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/* NOTE: Tentatively, Max77620 "mostly" matches https://datasheets.maximintegrated.com/en/ds/MAX77863.pdf. */
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/* NOTE: Tentatively, Max77620 "mostly" matches https://datasheets.maximintegrated.com/en/ds/MAX77863.pdf. */
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/* This does not contain Max77621 documentation, though. */
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/* This does not contain Max77621 documentation, though. */
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constexpr inline int Max77620RegisterGpio0 = 0x36;
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constexpr inline int Max77620RegisterOnOffStat = 0x15;
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constexpr inline int Max77620RegisterAmeGpio = 0x40;
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constexpr inline int Max77620RegisterGpio0 = 0x36;
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constexpr inline int Max77620RegisterAmeGpio = 0x40;
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constexpr inline int Max77620RegisterOnOffCnfg1 = 0x41;
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constexpr inline int Max77621RegisterVOut = 0x00;
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constexpr inline int Max77621RegisterVOut = 0x00;
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constexpr inline int Max77621RegisterVOutDvc = 0x01;
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constexpr inline int Max77621RegisterVOutDvc = 0x01;
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@ -108,6 +112,10 @@ namespace ams::pmic {
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}
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}
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}
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}
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u8 GetPmicOnOffStat() {
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return i2c::QueryByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterOnOffStat);
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}
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}
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}
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void EnableVddCpu(Regulator regulator) {
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void EnableVddCpu(Regulator regulator) {
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@ -132,4 +140,19 @@ namespace ams::pmic {
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}
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}
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}
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}
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void EnableSleep() {
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/* Get the current onoff cfg. */
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u8 cnfg = i2c::QueryByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterOnOffCnfg1);
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/* Set SlpEn. */
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cnfg |= (1 << 2);
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/* Write the new cfg. */
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i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterOnOffCnfg1, cnfg);
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}
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bool IsAcOk() {
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return (GetPmicOnOffStat() & (1 << 1)) != 0;
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}
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}
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}
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