From a64b838b9cbd7f939945a83dbf0865944aec5771 Mon Sep 17 00:00:00 2001 From: Michael Scire Date: Wed, 1 Sep 2021 18:10:48 -0700 Subject: [PATCH] fusee_cpp: implement cpu startup --- libexosphere/include/exosphere/clkrst.hpp | 1 + .../include/exosphere/hw/hw_arm64_cache.hpp | 1 + libexosphere/source/clkrst/clkrst_api.cpp | 10 ++++++++-- .../source/hw/hw_cache.arch.arm64.cpp | 11 +++++++++++ libexosphere/source/pmic/pmic_api.cpp | 6 +++--- .../include/vapours/tegra/tegra_clkrst.hpp | 19 +++++++++++++++++++ 6 files changed, 43 insertions(+), 5 deletions(-) diff --git a/libexosphere/include/exosphere/clkrst.hpp b/libexosphere/include/exosphere/clkrst.hpp index 3f344b25..dea47c18 100644 --- a/libexosphere/include/exosphere/clkrst.hpp +++ b/libexosphere/include/exosphere/clkrst.hpp @@ -31,6 +31,7 @@ namespace ams::clkrst { void EnableSeClock(); void EnableCldvfsClock(); + void EnableCsiteClock(); void EnableTzramClock(); void EnableCache2Clock(); diff --git a/libexosphere/include/exosphere/hw/hw_arm64_cache.hpp b/libexosphere/include/exosphere/hw/hw_arm64_cache.hpp index 547014f4..f489f739 100644 --- a/libexosphere/include/exosphere/hw/hw_arm64_cache.hpp +++ b/libexosphere/include/exosphere/hw/hw_arm64_cache.hpp @@ -53,5 +53,6 @@ namespace ams::hw::arch::arm64 { } void FlushDataCache(const void *ptr, size_t size); + void InvalidateDataCache(const void *ptr, size_t size); } \ No newline at end of file diff --git a/libexosphere/source/clkrst/clkrst_api.cpp b/libexosphere/source/clkrst/clkrst_api.cpp index 30c91949..583f3d7d 100644 --- a/libexosphere/source/clkrst/clkrst_api.cpp +++ b/libexosphere/source/clkrst/clkrst_api.cpp @@ -87,11 +87,13 @@ namespace ams::clkrst { DEFINE_CLOCK_PARAMETERS(SeClock, V, SE, PLLP_OUT0, 0); DEFINE_CLOCK_PARAMETERS(ActmonClock, V, ACTMON, CLK_M, 0); + DEFINE_CLOCK_PARAMETERS(CsiteClock, U, CSITE, PLLP_OUT0, 4); DEFINE_CLOCK_PARAMETERS(Host1xClock, L, HOST1X, PLLP_OUT0, 3); - DEFINE_CLOCK_PARAMETERS(TsecClock, U, TSEC, PLLP_OUT0, 2); - DEFINE_CLOCK_PARAMETERS(Sor1Clock, X, SOR1, PLLP_OUT0, 2); + DEFINE_CLOCK_PARAMETERS(TsecClock, U, TSEC, PLLP_OUT0, 2); + DEFINE_CLOCK_PARAMETERS(Sor1Clock, X, SOR1, PLLP_OUT0, 2); DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(CldvfsClock, W, DVFS); + DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(TzramClock, V, TZRAM); DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(SorSafeClock, Y, SOR_SAFE); @@ -203,6 +205,10 @@ namespace ams::clkrst { EnableClock(CldvfsClock); } + void EnableCsiteClock() { + EnableClock(CsiteClock); + } + void EnableTzramClock() { EnableClock(TzramClock); } diff --git a/libexosphere/source/hw/hw_cache.arch.arm64.cpp b/libexosphere/source/hw/hw_cache.arch.arm64.cpp index be19c118..1ad7a4bd 100644 --- a/libexosphere/source/hw/hw_cache.arch.arm64.cpp +++ b/libexosphere/source/hw/hw_cache.arch.arm64.cpp @@ -26,4 +26,15 @@ namespace ams::hw::arch::arm64 { } } + + + void InvalidateDataCache(const void *ptr, size_t size) { + const uintptr_t start = reinterpret_cast(ptr); + const uintptr_t end = util::AlignUp(start + size, hw::DataCacheLineSize); + + for (uintptr_t cur = start; cur < end; cur += hw::DataCacheLineSize) { + InvalidateDataCacheLine(reinterpret_cast(cur)); + } + } + } \ No newline at end of file diff --git a/libexosphere/source/pmic/pmic_api.cpp b/libexosphere/source/pmic/pmic_api.cpp index 47b86244..fdc0809d 100644 --- a/libexosphere/source/pmic/pmic_api.cpp +++ b/libexosphere/source/pmic/pmic_api.cpp @@ -65,13 +65,13 @@ namespace ams::pmic { u8 val; /* Clear the AE for the GPIO */ - if (i2c::Query(std::addressof(val), sizeof(val), i2c::Port_5, I2cAddressEristaMax77621, Max77620RegisterAmeGpio)) { + if (i2c::Query(std::addressof(val), sizeof(val), i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterAmeGpio)) { val &= ~(1 << gpio); - i2c::SendByte(i2c::Port_5, I2cAddressEristaMax77621, Max77620RegisterAmeGpio, val); + i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterAmeGpio, val); } /* Set GPIO_DRV_PUSHPULL (bit 0), GPIO_OUTPUT_VAL_HIGH (bit 3). */ - i2c::SendByte(i2c::Port_5, I2cAddressEristaMax77621, Max77620RegisterGpio0 + gpio, MAX77620_CNFG_GPIO_DRV_PUSHPULL | MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH); + i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterGpio0 + gpio, MAX77620_CNFG_GPIO_DRV_PUSHPULL | MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH); } void SetEnBitErista() { diff --git a/libvapours/include/vapours/tegra/tegra_clkrst.hpp b/libvapours/include/vapours/tegra/tegra_clkrst.hpp index c34059c5..5911f56f 100644 --- a/libvapours/include/vapours/tegra/tegra_clkrst.hpp +++ b/libvapours/include/vapours/tegra/tegra_clkrst.hpp @@ -36,6 +36,8 @@ #define CLK_RST_CONTROLLER_RST_SOURCE (0x000) +#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY (0x020) +#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER (0x024) #define CLK_RST_CONTROLLER_SCLK_BURST_POLICY (0x028) #define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER (0x02C) #define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE (0x030) @@ -58,6 +60,9 @@ #define CLK_RST_CONTROLLER_CCLKLP_BURST_POLICY (0x370) #define CLK_RST_CONTROLLER_SUPER_CCLKLP_DIVIDER (0x374) #define CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2 (0x388) +#define CLK_RST_CONTROLLER_PLLX_MISC1 (0x510) +#define CLK_RST_CONTROLLER_PLLX_MISC2 (0x514) +#define CLK_RST_CONTROLLER_PLLX_MISC3 (0x518) #define CLK_RST_CONTROLLER_SPARE_REG0 (0x55C) #define CLK_RST_CONTROLLER_PLLC4_BASE (0x5A4) #define CLK_RST_CONTROLLER_PLLC_MISC2 (0x5D0) @@ -125,8 +130,12 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_PLLD_REF_DIS, 29, REF_ENABLE, REF_DISABLE) DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_PLLD_ENABLE, 30, DISABLE, ENABLE); DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_PLLD_BYPASS, 31, DISABLE, ENABLE); +DEFINE_CLK_RST_REG_BIT_ENUM(PLLX_BASE_PLLX_LOCK, 27, NOT_LOCK, LOCK); +DEFINE_CLK_RST_REG_BIT_ENUM(PLLX_BASE_PLLX_REF_DIS, 29, REF_ENABLE, REF_DISABLE); DEFINE_CLK_RST_REG_BIT_ENUM(PLLX_BASE_PLLX_ENABLE, 30, DISABLE, ENABLE); +DEFINE_CLK_RST_REG_BIT_ENUM(PLLX_MISC_PLLX_LOCK_ENABLE, 18, DISABLE, ENABLE); + DEFINE_CLK_RST_REG(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIVISOR, 0, 8); DEFINE_CLK_RST_REG(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIVIDEND, 8, 8); DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_CPU_IRQ, 24, NO_IMPACT, DISABLE); @@ -134,6 +143,8 @@ DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_COP_IRQ, 25, DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_CPU_FIQ, 26, NO_IMPACT, DISABLE); DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_COP_FIQ, 27, NO_IMPACT, DISABLE); +DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB, 31, DISABLE, ENABLE); + DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLKG_DIVIDER_SUPER_CDIV_ENB, 31, DISABLE, ENABLE); DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLKLP_DIVIDER_SUPER_CDIV_ENB, 31, DISABLE, ENABLE); @@ -145,6 +156,8 @@ DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CPU_STATE, 28, STDB DEFINE_CLK_RST_REG(CPU_SOFTRST_CTRL2_CAR2PMC_CPU_ACK_WIDTH, 0, 12); +DEFINE_CLK_RST_REG(PLLX_MISC3_PLLX_IDDQ, 3, 1); + DEFINE_CLK_RST_REG_TWO_BIT_ENUM(SPARE_REG0_CLK_M_DIVISOR, 2, CLK_M_DIVISOR1, CLK_M_DIVISOR2, CLK_M_DIVISOR3, CLK_M_DIVISOR4); DEFINE_CLK_RST_REG_BIT_ENUM(PLLC4_BASE_PLLC4_IDDQ, 18, OFF, ON); @@ -286,6 +299,8 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLMB_BASE_PLLMB_ENABLE, 30, DISABLE, ENABLE); #define CLK_RST_CONTROLLER_CLK_ENB_SE_INDEX (0x1F) +#define CLK_RST_CONTROLLER_CLK_ENB_CSITE_INDEX (0x09) + #define CLK_RST_CONTROLLER_CLK_ENB_HOST1X_INDEX (0x1C) #define CLK_RST_CONTROLLER_CLK_ENB_TSEC_INDEX (0x13) #define CLK_RST_CONTROLLER_CLK_ENB_SOR0_INDEX (0x16) @@ -344,6 +359,8 @@ DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, 29, PLLM_OUT0, DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_NVENC_NVENC_CLK_SRC, 29, RESERVED0, PLLC2_OUT0, PLLC_OUT0, PLLC3_OUT0, PLLP_OUT0, RESERVED5, PLLA1_OUT0, CLK_M); +DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_CSITE_CSITE_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC3_OUT0, PLLREFE_OUT1, PLLA1_OUT0, CLK_M, PLLC4_OUT0); + DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_TSEC_TSEC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC3_OUT0, RESERVED4, PLLA1_OUT0, CLK_M, PLLC4_OUT0); DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_SE_SE_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC3_OUT0, RSVD4, PLLA1_OUT0, CLK_M, PLLC4_OUT0); @@ -386,7 +403,9 @@ DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET0, 16, DISABLE, ENA DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET1, 17, DISABLE, ENABLE); DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET2, 18, DISABLE, ENABLE); DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET3, 19, DISABLE, ENABLE); +DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_L2RESET, 24, DISABLE, ENABLE); DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_NONCPURESET, 29, DISABLE, ENABLE); +DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_PRESETDBG, 30, DISABLE, ENABLE); /* TODO: Actually include all devices. */ #define CLK_RST_FOREACH_DEVICE(HANDLER) \