From 9819c15c5bd85874214b17be3dc9725e84628160 Mon Sep 17 00:00:00 2001 From: Michael Scire Date: Thu, 14 May 2020 15:57:22 -0700 Subject: [PATCH] exo2: Implement SmcReadWriteRegister --- .../include/exosphere/tegra/tegra_mc.hpp | 214 +++++++++++++++++- .../include/exosphere/tegra/tegra_pmc.hpp | 155 +++++++------ 2 files changed, 294 insertions(+), 75 deletions(-) diff --git a/libexosphere/include/exosphere/tegra/tegra_mc.hpp b/libexosphere/include/exosphere/tegra/tegra_mc.hpp index 7f309daf..72947de8 100644 --- a/libexosphere/include/exosphere/tegra/tegra_mc.hpp +++ b/libexosphere/include/exosphere/tegra/tegra_mc.hpp @@ -17,17 +17,186 @@ #include #include -#define MC_INTSTATUS (0x000) -#define MC_INTMASK (0x004) -#define MC_ERR_STATUS (0x008) -#define MC_ERR_ADR (0x00c) -#define MC_SMMU_CONFIG (0x010) +#define MC_INTSTATUS (0x000) +#define MC_INTMASK (0x004) +#define MC_ERR_STATUS (0x008) +#define MC_ERR_ADR (0x00C) +#define MC_SMMU_CONFIG (0x010) +#define MC_SMMU_PTB_ASID (0x01C) +#define MC_SMMU_PTB_DATA (0x020) +#define MC_SMMU_TLB_FLUSH (0x030) +#define MC_SMMU_PTC_FLUSH (0x034) +#define MC_EMEM_CFG (0x050) +#define MC_EMEM_ADR_CFG (0x054) +#define MC_EMEM_ARB_CFG (0x090) +#define MC_EMEM_ARB_OUTSTANDING_REQ (0x094) +#define MC_EMEM_ARB_TIMING_RCD (0x098) +#define MC_EMEM_ARB_TIMING_RP (0x09C) +#define MC_EMEM_ARB_TIMING_RC (0x0A0) +#define MC_EMEM_ARB_TIMING_RAS (0x0A4) +#define MC_EMEM_ARB_TIMING_FAW (0x0A8) +#define MC_EMEM_ARB_TIMING_RRD (0x0AC) +#define MC_EMEM_ARB_TIMING_RAP2PRE (0x0B0) +#define MC_EMEM_ARB_TIMING_WAP2PRE (0x0B4) +#define MC_EMEM_ARB_TIMING_R2R (0x0B8) +#define MC_EMEM_ARB_TIMING_W2W (0x0BC) +#define MC_EMEM_ARB_TIMING_R2W (0x0C0) +#define MC_EMEM_ARB_TIMING_W2R (0x0C4) +#define MC_EMEM_ARB_MISC2 (0x0C8) +#define MC_EMEM_ARB_DA_TURNS (0x0D0) +#define MC_EMEM_ARB_DA_COVERS (0x0D4) +#define MC_EMEM_ARB_MISC0 (0x0D8) +#define MC_EMEM_ARB_MISC1 (0x0DC) +#define MC_EMEM_ARB_RING1_THROTTLE (0x0E0) +#define MC_CLIENT_HOTRESET_CTRL (0x200) +#define MC_CLIENT_HOTRESET_STATUS (0x204) +#define MC_SMMU_AFI_ASID (0x238) +#define MC_SMMU_DC_ASID (0x240) +#define MC_SMMU_DCB_ASID (0x244) +#define MC_SMMU_HC_ASID (0x250) +#define MC_SMMU_HDA_ASID (0x254) +#define MC_SMMU_ISP2_ASID (0x258) +#define MC_SMMU_NVENC_ASID (0x264) +#define MC_SMMU_NV_ASID (0x268) +#define MC_SMMU_NV2_ASID (0x26C) +#define MC_SMMU_PPCS_ASID (0x270) +#define MC_SMMU_SATA_ASID (0x274) +#define MC_SMMU_VI_ASID (0x280) +#define MC_SMMU_VIC_ASID (0x284) +#define MC_SMMU_XUSB_HOST_ASID (0x288) +#define MC_SMMU_XUSB_DEV_ASID (0x28C) +#define MC_SMMU_TSEC_ASID (0x294) +#define MC_LATENCY_ALLOWANCE_AVPC_0 (0x2E4) +#define MC_LATENCY_ALLOWANCE_DC_0 (0x2E8) +#define MC_LATENCY_ALLOWANCE_DC_1 (0x2EC) +#define MC_LATENCY_ALLOWANCE_DCB_0 (0x2F4) +#define MC_LATENCY_ALLOWANCE_DCB_1 (0x2F8) +#define MC_LATENCY_ALLOWANCE_HC_0 (0x310) +#define MC_LATENCY_ALLOWANCE_HC_1 (0x314) +#define MC_LATENCY_ALLOWANCE_MPCORE_0 (0x320) +#define MC_LATENCY_ALLOWANCE_NVENC_0 (0x328) +#define MC_LATENCY_ALLOWANCE_PPCS_0 (0x344) +#define MC_LATENCY_ALLOWANCE_PPCS_1 (0x348) +#define MC_LATENCY_ALLOWANCE_ISP2_0 (0x370) +#define MC_LATENCY_ALLOWANCE_ISP2_1 (0x374) +#define MC_LATENCY_ALLOWANCE_XUSB_0 (0x37C) +#define MC_LATENCY_ALLOWANCE_XUSB_1 (0x380) +#define MC_LATENCY_ALLOWANCE_TSEC_0 (0x390) +#define MC_LATENCY_ALLOWANCE_VIC_0 (0x394) +#define MC_LATENCY_ALLOWANCE_VI2_0 (0x398) +#define MC_LATENCY_ALLOWANCE_GPU_0 (0x3AC) +#define MC_LATENCY_ALLOWANCE_SDMMCA_0 (0x3B8) +#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 (0x3BC) +#define MC_LATENCY_ALLOWANCE_SDMMC_0 (0x3C0) +#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 (0x3C4) +#define MC_LATENCY_ALLOWANCE_NVDEC_0 (0x3D8) +#define MC_LATENCY_ALLOWANCE_GPU2_0 (0x3E8) +#define MC_DIS_PTSA_RATE (0x41C) +#define MC_DIS_PTSA_MIN (0x420) +#define MC_DIS_PTSA_MAX (0x424) +#define MC_DISB_PTSA_RATE (0x428) +#define MC_DISB_PTSA_MIN (0x42C) +#define MC_DISB_PTSA_MAX (0x430) +#define MC_VE_PTSA_RATE (0x434) +#define MC_VE_PTSA_MIN (0x438) +#define MC_VE_PTSA_MAX (0x43C) +#define MC_MLL_MPCORER_PTSA_RATE (0x44C) +#define MC_RING1_PTSA_RATE (0x47C) +#define MC_RING1_PTSA_MIN (0x480) +#define MC_RING1_PTSA_MAX (0x484) +#define MC_PCX_PTSA_RATE (0x4AC) +#define MC_PCX_PTSA_MIN (0x4B0) +#define MC_PCX_PTSA_MAX (0x4B4) +#define MC_MSE_PTSA_RATE (0x4C4) +#define MC_MSE_PTSA_MIN (0x4C8) +#define MC_MSE_PTSA_MAX (0x4CC) +#define MC_AHB_PTSA_RATE (0x4DC) +#define MC_AHB_PTSA_MIN (0x4E0) +#define MC_AHB_PTSA_MAX (0x4E4) +#define MC_APB_PTSA_RATE (0x4E8) +#define MC_APB_PTSA_MIN (0x4EC) +#define MC_APB_PTSA_MAX (0x4F0) +#define MC_FTOP_PTSA_RATE (0x50C) +#define MC_HOST_PTSA_RATE (0x518) +#define MC_HOST_PTSA_MIN (0x51C) +#define MC_HOST_PTSA_MAX (0x520) +#define MC_USBX_PTSA_RATE (0x524) +#define MC_USBX_PTSA_MIN (0x528) +#define MC_USBX_PTSA_MAX (0x52C) +#define MC_USBD_PTSA_RATE (0x530) +#define MC_USBD_PTSA_MIN (0x534) +#define MC_USBD_PTSA_MAX (0x538) +#define MC_GK_PTSA_RATE (0x53C) +#define MC_GK_PTSA_MIN (0x540) +#define MC_GK_PTSA_MAX (0x544) +#define MC_AUD_PTSA_RATE (0x548) +#define MC_AUD_PTSA_MIN (0x54C) +#define MC_AUD_PTSA_MAX (0x550) +#define MC_VICPC_PTSA_RATE (0x554) +#define MC_VICPC_PTSA_MIN (0x558) +#define MC_VICPC_PTSA_MAX (0x55C) +#define MC_JPG_PTSA_RATE (0x584) +#define MC_JPG_PTSA_MIN (0x588) +#define MC_JPG_PTSA_MAX (0x58C) +#define MC_GK2_PTSA_RATE (0x610) +#define MC_GK2_PTSA_MIN (0x614) +#define MC_GK2_PTSA_MAX (0x618) +#define MC_SDM_PTSA_RATE (0x61C) +#define MC_SDM_PTSA_MIN (0x620) +#define MC_SDM_PTSA_MAX (0x624) +#define MC_HDAPC_PTSA_RATE (0x628) +#define MC_HDAPC_PTSA_MIN (0x62C) +#define MC_HDAPC_PTSA_MAX (0x630) +#define MC_SEC_CARVEOUT_BOM (0x670) +#define MC_SEC_CARVEOUT_SIZE_MB (0x674) +#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A (0x690) +#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB (0x694) +#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B (0x698) +#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB (0x69C) +#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C (0x6A0) +#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB (0x6A4) +#define MC_EMEM_ARB_TIMING_RFCPB (0x6C0) +#define MC_EMEM_ARB_TIMING_CCDMW (0x6C4) +#define MC_EMEM_ARB_REFPB_HP_CTRL (0x6F0) +#define MC_EMEM_ARB_REFPB_BANK_CTRL (0x6F4) +#define MC_PTSA_GRANT_DECREMENT (0x960) +#define MC_CLIENT_HOTRESET_CTRL_1 (0x970) +#define MC_CLIENT_HOTRESET_STATUS_1 (0x974) +#define MC_SMMU_PTC_FLUSH_1 (0x9B8) +#define MC_SMMU_DC1_ASID (0xA88) +#define MC_SMMU_SDMMC1A_ASID (0xA94) +#define MC_SMMU_SDMMC2A_ASID (0xA98) +#define MC_SMMU_SDMMC3A_ASID (0xA9C) +#define MC_SMMU_SDMMC4A_ASID (0xAA0) +#define MC_SMMU_ISP2B_ASID (0xAA4) +#define MC_SMMU_GPU_ASID (0xAA8) +#define MC_SMMU_GPUB_ASID (0xAAC) +#define MC_SMMU_PPCS2_ASID (0xAB0) +#define MC_SMMU_NVDEC_ASID (0xAB4) +#define MC_SMMU_APE_ASID (0xAB8) +#define MC_SMMU_SE_ASID (0xABC) +#define MC_SMMU_NVJPG_ASID (0xAC0) +#define MC_SMMU_HC1_ASID (0xAC4) +#define MC_SMMU_SE1_ASID (0xAC8) +#define MC_SMMU_AXIAP_ASID (0xACC) +#define MC_SMMU_ETR_ASID (0xAD0) +#define MC_SMMU_TSECB_ASID (0xAD4) +#define MC_SMMU_TSEC1_ASID (0xAD8) +#define MC_SMMU_TSECB1_ASID (0xADC) +#define MC_SMMU_NVDEC1_ASID (0xAE0) +#define MC_EMEM_ARB_DHYST_CTRL (0xBCC) +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 (0xBD0) +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 (0xBD4) +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 (0xBD8) +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 (0xBDC) +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 (0xBE0) +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 (0xBE4) +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 (0xBE8) +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 (0xBEC) +#define MC_ERR_GENERALIZED_CARVEOUT_STATUS (0xC00) + #define MC_SMMU_TLB_CONFIG (0x014) #define MC_SMMU_PTC_CONFIG (0x018) -#define MC_SMMU_PTB_ASID (0x01c) -#define MC_SMMU_PTB_DATA (0x020) -#define MC_SMMU_TLB_FLUSH (0x030) -#define MC_SMMU_PTC_FLUSH (0x034) #define MC_SMMU_AVPC_ASID (0x23C) #define MC_SMMU_PPCS1_ASID (0x298) @@ -145,6 +314,33 @@ #define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3 (0xd78) #define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4 (0xd7c) +#define MC_STAT_CONTROL (0x100) +#define MC_STAT_EMC_CLOCK_LIMIT (0x108) +#define MC_STAT_EMC_CLOCK_LIMIT_MSBS (0x10c) +#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO (0x118) +#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI (0x11c) +#define MC_STAT_EMC_FILTER_SET0_SPARE (0x124) +#define MC_STAT_EMC_FILTER_SET0_CLIENT_0 (0x128) +#define MC_STAT_EMC_FILTER_SET0_CLIENT_1 (0x12c) +#define MC_STAT_EMC_FILTER_SET0_CLIENT_2 (0x130) +#define MC_STAT_EMC_FILTER_SET0_CLIENT_3 (0x134) +#define MC_STAT_EMC_SET0_COUNT (0x138) +#define MC_STAT_EMC_SET0_COUNT_MSBS (0x13c) +#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO (0x158) +#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI (0x15c) +#define MC_STAT_EMC_FILTER_SET1_SPARE (0x164) +#define MC_STAT_EMC_FILTER_SET1_CLIENT_0 (0x168) +#define MC_STAT_EMC_FILTER_SET1_CLIENT_1 (0x16c) +#define MC_STAT_EMC_FILTER_SET1_CLIENT_2 (0x170) +#define MC_STAT_EMC_FILTER_SET1_CLIENT_3 (0x174) +#define MC_STAT_EMC_SET1_COUNT (0x178) +#define MC_STAT_EMC_SET1_COUNT_MSBS (0x17c) +#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER (0xa20) +#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER (0xa24) +#define MC_STAT_EMC_FILTER_SET0_CLIENT_4 (0xb88) +#define MC_STAT_EMC_FILTER_SET1_CLIENT_4 (0xb8c) +#define MC_STAT_EMC_FILTER_SET0_CLIENT_5 (0xbc4) +#define MC_STAT_EMC_FILTER_SET1_CLIENT_5 (0xbc8) #define MC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (MC, NAME) #define MC_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (MC, NAME, VALUE) diff --git a/libexosphere/include/exosphere/tegra/tegra_pmc.hpp b/libexosphere/include/exosphere/tegra/tegra_pmc.hpp index 27a80956..3f1d90ed 100644 --- a/libexosphere/include/exosphere/tegra/tegra_pmc.hpp +++ b/libexosphere/include/exosphere/tegra/tegra_pmc.hpp @@ -17,72 +17,95 @@ #include #include -#define APBDEV_PMC_CNTRL (0x000) -#define APBDEV_PMC_DPD_SAMPLE (0x020) -#define APBDEV_PMC_DPD_ENABLE (0x024) -#define APBDEV_PMC_CLAMP_STATUS (0x02C) -#define APBDEV_PMC_PWRGATE_TOGGLE (0x030) -#define APBDEV_PMC_PWRGATE_STATUS (0x038) -#define APBDEV_PMC_SCRATCH0 (0x050) -#define APBDEV_PMC_SCRATCH1 (0x054) -#define APBDEV_PMC_SCRATCH12 (0x080) -#define APBDEV_PMC_SCRATCH13 (0x084) -#define APBDEV_PMC_SCRATCH18 (0x098) -#define APBDEV_PMC_SCRATCH20 (0x0A0) -#define APBDEV_PMC_CRYPTO_OP (0x0F4) -#define APBDEV_PM (0x014) -#define APBDEV_PMC_WAKE2_STATUS (0x168) -#define APBDEV_PMC_WEAK_BIAS (0x2C8) -#define APBDEV_PMC_CNTRL2 (0x440) -#define APBDEV_PMC_FUSE_CTRL (0x450) -#define APBDEV_PMC_IO_DPD3_REQ (0x45C) -#define APBDEV_PMC_IO_DPD3_STATUS (0x460) -#define APBDEV_PMC_IO_DPD4_REQ (0x464) -#define APBDEV_PMC_IO_DPD4_STATUS (0x468) -#define APBDEV_PMC_SET_SW_CLAMP (0x47C) -#define APBDEV_PMC_DDR_CNTRL (0x4E4) -#define APBDEV_PMC_SEC_DISABLE (0x004) -#define APBDEV_PMC_SEC_DISABLE2 (0x2C4) -#define APBDEV_PMC_SEC_DISABLE3 (0x2D8) -#define APBDEV_PMC_SEC_DISABLE4 (0x5B0) -#define APBDEV_PMC_SEC_DISABLE5 (0x5B4) -#define APBDEV_PMC_SEC_DISABLE6 (0x5B8) -#define APBDEV_PMC_SEC_DISABLE7 (0x5BC) -#define APBDEV_PMC_SEC_DISABLE8 (0x5C0) -#define APBDEV_PMC_SCRATCH43 (0x22C) -#define APBDEV_PMC_SCRATCH190 (0x818) -#define APBDEV_PMC_SCRATCH200 (0x840) -#define APBDEV_PMC_SEC_DISABLE3 (0x2D8) -#define APBDEV_PMC_SECURE_SCRATCH4 (0x0C0) -#define APBDEV_PMC_SECURE_SCRATCH5 (0x0C4) -#define APBDEV_PMC_SECURE_SCRATCH6 (0x224) -#define APBDEV_PMC_SECURE_SCRATCH7 (0x228) -#define APBDEV_PMC_SECURE_SCRATCH16 (0x320) -#define APBDEV_PMC_SECURE_SCRATCH21 (0x334) -#define APBDEV_PMC_SECURE_SCRATCH24 (0x340) -#define APBDEV_PMC_SECURE_SCRATCH25 (0x344) -#define APBDEV_PMC_SECURE_SCRATCH26 (0x348) -#define APBDEV_PMC_SECURE_SCRATCH27 (0x34C) -#define APBDEV_PMC_SECURE_SCRATCH32 (0x360) -#define APBDEV_PMC_SECURE_SCRATCH34 (0x368) -#define APBDEV_PMC_SECURE_SCRATCH35 (0x36C) -#define APBDEV_PMC_SECURE_SCRATCH39 (0x37C) -#define APBDEV_PMC_SECURE_SCRATCH51 (0x3AC) -#define APBDEV_PMC_SECURE_SCRATCH55 (0x3BC) -#define APBDEV_PMC_SECURE_SCRATCH74 (0x408) -#define APBDEV_PMC_SECURE_SCRATCH75 (0x40C) -#define APBDEV_PMC_SECURE_SCRATCH76 (0x410) -#define APBDEV_PMC_SECURE_SCRATCH77 (0x414) -#define APBDEV_PMC_SECURE_SCRATCH78 (0x418) -#define APBDEV_PMC_SECURE_SCRATCH99 (0xAE4) -#define APBDEV_PMC_SECURE_SCRATCH100 (0xAE8) -#define APBDEV_PMC_SECURE_SCRATCH101 (0xAEC) -#define APBDEV_PMC_SECURE_SCRATCH102 (0xAF0) -#define APBDEV_PMC_SECURE_SCRATCH103 (0xAF4) -#define APBDEV_PMC_SECURE_SCRATCH112 (0xB18) -#define APBDEV_PMC_SECURE_SCRATCH113 (0xB1C) -#define APBDEV_PMC_SECURE_SCRATCH114 (0xB20) -#define APBDEV_PMC_SECURE_SCRATCH115 (0xB24) +#define APBDEV_PMC_CNTRL (0x000) +#define APBDEV_PMC_WAKE_MASK (0x00C) +#define APBDEV_PMC_WAKE_LVL (0x010) +#define APBDEV_PMC_WAKE_STATUS (0x014) +#define APBDEV_PMC_DPD_PADS_ORIDE (0x01C) +#define APBDEV_PMC_DPD_SAMPLE (0x020) +#define APBDEV_PMC_DPD_ENABLE (0x024) +#define APBDEV_PMC_CLAMP_STATUS (0x02C) +#define APBDEV_PMC_PWRGATE_TOGGLE (0x030) +#define APBDEV_PMC_REMOVE_CLAMPING_CMD (0x034) +#define APBDEV_PMC_PWRGATE_STATUS (0x038) +#define APBDEV_PMC_PWRGOOD_TIMER (0x03C) +#define APBDEV_PMC_BLINK_TIMER (0x040) +#define APBDEV_PMC_NO_IOPOWER (0x044) +#define APBDEV_PMC_PWR_DET (0x048) +#define APBDEV_PMC_SCRATCH0 (0x050) +#define APBDEV_PMC_SCRATCH1 (0x054) +#define APBDEV_PMC_SCRATCH12 (0x080) +#define APBDEV_PMC_SCRATCH13 (0x084) +#define APBDEV_PMC_SCRATCH18 (0x098) +#define APBDEV_PMC_SCRATCH20 (0x0A0) +#define APBDEV_PMC_AUTO_WAKE_LVL_MASK (0x0DC) +#define APBDEV_PMC_WAKE_DELAY (0x0E0) +#define APBDEV_PMC_PWR_DET_VAL (0x0E4) +#define APBDEV_PMC_CRYPTO_OP (0x0F4) +#define APBDEV_PMC_WAKE2_MASK (0x160) +#define APBDEV_PMC_WAKE2_LVL (0x164) +#define APBDEV_PMC_WAKE2_STATUS (0x168) +#define APBDEV_PMC_AUTO_WAKE2_LVL_MASK (0x170) +#define APBDEV_PMC_CLK_OUT_CNTRL (0x1A8) +#define APBDEV_PMC_IO_DPD_REQ (0x1B8) +#define APBDEV_PMC_IO_DPD_STATUS (0x1BC) +#define APBDEV_PMC_IO_DPD2_REQ (0x1C0) +#define APBDEV_PMC_IO_DPD2_STATUS (0x1C4) +#define APBDEV_PMC_SEL_DPD_TIM (0x1C8) +#define APBDEV_PMC_TSC_MULT (0x2B4) +#define APBDEV_PMC_WEAK_BIAS (0x2C8) +#define APBDEV_PMC_GPU_RG_CNTRL (0x2D4) +#define APBDEV_PMC_CNTRL2 (0x440) +#define APBDEV_PMC_FUSE_CTRL (0x450) +#define APBDEV_PMC_IO_DPD3_REQ (0x45C) +#define APBDEV_PMC_IO_DPD3_STATUS (0x460) +#define APBDEV_PMC_IO_DPD4_REQ (0x464) +#define APBDEV_PMC_IO_DPD4_STATUS (0x468) +#define APBDEV_PMC_SET_SW_CLAMP (0x47C) +#define APBDEV_PMC_WAKE_DEBOUNCE_EN (0x4D8) +#define APBDEV_PMC_DDR_CNTRL (0x4E4) +#define APBDEV_PMC_SEC_DISABLE (0x004) +#define APBDEV_PMC_SEC_DISABLE2 (0x2C4) +#define APBDEV_PMC_SEC_DISABLE3 (0x2D8) +#define APBDEV_PMC_SEC_DISABLE4 (0x5B0) +#define APBDEV_PMC_SEC_DISABLE5 (0x5B4) +#define APBDEV_PMC_SEC_DISABLE6 (0x5B8) +#define APBDEV_PMC_SEC_DISABLE7 (0x5BC) +#define APBDEV_PMC_SEC_DISABLE8 (0x5C0) +#define APBDEV_PMC_SCRATCH43 (0x22C) +#define APBDEV_PMC_SCRATCH190 (0x818) +#define APBDEV_PMC_SCRATCH200 (0x840) +#define APBDEV_PMC_SEC_DISABLE3 (0x2D8) +#define APBDEV_PMC_SECURE_SCRATCH4 (0x0C0) +#define APBDEV_PMC_SECURE_SCRATCH5 (0x0C4) +#define APBDEV_PMC_SECURE_SCRATCH6 (0x224) +#define APBDEV_PMC_SECURE_SCRATCH7 (0x228) +#define APBDEV_PMC_SECURE_SCRATCH16 (0x320) +#define APBDEV_PMC_SECURE_SCRATCH21 (0x334) +#define APBDEV_PMC_SECURE_SCRATCH24 (0x340) +#define APBDEV_PMC_SECURE_SCRATCH25 (0x344) +#define APBDEV_PMC_SECURE_SCRATCH26 (0x348) +#define APBDEV_PMC_SECURE_SCRATCH27 (0x34C) +#define APBDEV_PMC_SECURE_SCRATCH32 (0x360) +#define APBDEV_PMC_SECURE_SCRATCH34 (0x368) +#define APBDEV_PMC_SECURE_SCRATCH35 (0x36C) +#define APBDEV_PMC_SECURE_SCRATCH39 (0x37C) +#define APBDEV_PMC_SECURE_SCRATCH51 (0x3AC) +#define APBDEV_PMC_SECURE_SCRATCH55 (0x3BC) +#define APBDEV_PMC_SECURE_SCRATCH74 (0x408) +#define APBDEV_PMC_SECURE_SCRATCH75 (0x40C) +#define APBDEV_PMC_SECURE_SCRATCH76 (0x410) +#define APBDEV_PMC_SECURE_SCRATCH77 (0x414) +#define APBDEV_PMC_SECURE_SCRATCH78 (0x418) +#define APBDEV_PMC_SECURE_SCRATCH99 (0xAE4) +#define APBDEV_PMC_SECURE_SCRATCH100 (0xAE8) +#define APBDEV_PMC_SECURE_SCRATCH101 (0xAEC) +#define APBDEV_PMC_SECURE_SCRATCH102 (0xAF0) +#define APBDEV_PMC_SECURE_SCRATCH103 (0xAF4) +#define APBDEV_PMC_SECURE_SCRATCH112 (0xB18) +#define APBDEV_PMC_SECURE_SCRATCH113 (0xB1C) +#define APBDEV_PMC_SECURE_SCRATCH114 (0xB20) +#define APBDEV_PMC_SECURE_SCRATCH115 (0xB24) #define PMC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (APBDEV_PMC, NAME)