diff --git a/libvapours/include/vapours/reg.hpp b/libvapours/include/vapours/reg.hpp
index 7cf77031..d8e6be43 100644
--- a/libvapours/include/vapours/reg.hpp
+++ b/libvapours/include/vapours/reg.hpp
@@ -56,6 +56,12 @@ namespace ams::reg {
         return (EncodeMask(masks) | ...);
     }
 
+    template<typename IntType> requires UnsignedNonConstIntegral<IntType>
+    constexpr ALWAYS_INLINE IntType GetField(const IntType &value, const BitsMask mask) { return (value & EncodeMask(mask)) >> GetOffset(mask); }
+
+    template<typename IntType> requires UnsignedNonConstIntegral<IntType>
+    constexpr ALWAYS_INLINE void SetField(IntType &value, const BitsValue v) { value = (value & ~EncodeMask(v)) | EncodeValue(v); }
+
     template<typename IntType> requires UnsignedNonConstIntegral<IntType>
     ALWAYS_INLINE void Write(volatile IntType *reg, std::type_identity_t<IntType> val) { *reg = val; }
 
diff --git a/libvapours/include/vapours/tegra/tegra_clkrst.hpp b/libvapours/include/vapours/tegra/tegra_clkrst.hpp
index b1f8a859..bd3a660b 100644
--- a/libvapours/include/vapours/tegra/tegra_clkrst.hpp
+++ b/libvapours/include/vapours/tegra/tegra_clkrst.hpp
@@ -118,6 +118,8 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_REF_DIS, 29, REF_ENABLE, REF_DISABLE)
 DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_ENABLE, 30, DISABLE, ENABLE);
 DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_BYPASSPLL, 31, DISABLE, ENABLE);
 
+DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_MISC2_PLLM_EN_LCKDET, 4, DISABLE, ENABLE);
+
 DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_CSI_CLK_SRC,  23, BRICK, PLL_D);
 DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_PLLD_REF_DIS, 29, REF_ENABLE, REF_DISABLE);
 DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_PLLD_ENABLE,  30, DISABLE, ENABLE);
@@ -149,6 +151,10 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLC4_BASE_PLLC4_IDDQ,   18, OFF, ON);
 DEFINE_CLK_RST_REG_BIT_ENUM(PLLC4_BASE_PLLC4_LOCK,   27, NOT_LOCK, LOCK_FEQ_AND_PHASE);
 DEFINE_CLK_RST_REG_BIT_ENUM(PLLC4_BASE_PLLC4_ENABLE, 30, DISABLE, ENABLE);
 
+DEFINE_CLK_RST_REG(PLLMB_BASE_PLLMB_DIVM, 0, 8);
+DEFINE_CLK_RST_REG(PLLMB_BASE_PLLMB_DIVN, 8, 8);
+DEFINE_CLK_RST_REG(PLLMB_BASE_PLLMB_DIVP, 20, 5);
+DEFINE_CLK_RST_REG_BIT_ENUM(PLLMB_BASE_PLLMB_LOCK, 27, NOT_LOCK, LOCK);
 DEFINE_CLK_RST_REG_BIT_ENUM(PLLMB_BASE_PLLMB_ENABLE, 30, DISABLE, ENABLE);
 
 /* RST_DEVICES */
@@ -332,6 +338,7 @@ DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_VI_VI_CLK_SRC, 29, RESERVED0, PLLC2
 
 DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_HOST1X_HOST1X_CLK_SRC, 29, PLLC4_OUT1, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT2, PLLP_OUT0, CLK_M, PLLA_OUT0, PLLC4_OUT0);
 
+DEFINE_CLK_RST_REG(CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR, 0, 8);
 DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, 29, PLLM_OUT0, PLLC_OUT0, PLLP_OUT0, CLK_M, PLLM_UD, PLLMB_UD, PLLMB_OUT0, PLLP_UD);
 
 DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_NVENC_NVENC_CLK_SRC, 29, RESERVED0, PLLC2_OUT0, PLLC_OUT0, PLLC3_OUT0, PLLP_OUT0, RESERVED5, PLLA1_OUT0, CLK_M);