From 72a7b840d35c71f3742ed4ac9e5dec5be8a29a8d Mon Sep 17 00:00:00 2001 From: Michael Scire Date: Sun, 7 Jun 2020 19:51:49 -0700 Subject: [PATCH] exo2: add sc7fw load, skeleton rest of suspend --- libexosphere/include/exosphere/tegra/tegra_clkrst.hpp | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/libexosphere/include/exosphere/tegra/tegra_clkrst.hpp b/libexosphere/include/exosphere/tegra/tegra_clkrst.hpp index 3659194a..f6a1ae6b 100644 --- a/libexosphere/include/exosphere/tegra/tegra_clkrst.hpp +++ b/libexosphere/include/exosphere/tegra/tegra_clkrst.hpp @@ -61,7 +61,10 @@ DEFINE_CLK_RST_REG(MISC_CLK_ENB_CFG_ALL_VISIBLE, 28, 1); #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA (0x178) #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB (0x17C) #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC (0x1A0) -#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON (0x3e8) +#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON (0x3E8) + +/* RST_DEV_*_CLR */ +#define CLK_RST_CONTROLLER_RST_DEV_L_CLR (0x304) /* CLK_ENB_*_INDEX */ #define CLK_RST_CONTROLLER_CLK_ENB_I2C1_INDEX (0x0C) @@ -96,3 +99,5 @@ DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTB_UARTB_CLK_SRC, 29, PLLP_OUT0, DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTC_UARTC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2); DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_ACTMON_ACTMON_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, CLK_S, PLLC4_OUT1, CLK_M, PLLC4_OUT2); + +DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_L_CLR_CLR_COP_RST, 1, DISABLE, ENABLE);