diff --git a/libexosphere/include/exosphere/clkrst.hpp b/libexosphere/include/exosphere/clkrst.hpp index c26dfb11..2f014397 100644 --- a/libexosphere/include/exosphere/clkrst.hpp +++ b/libexosphere/include/exosphere/clkrst.hpp @@ -25,5 +25,6 @@ namespace ams::clkrst { void EnableUartAClock(); void EnableUartBClock(); void EnableUartCClock(); + void EnableActmonClock(); } \ No newline at end of file diff --git a/libexosphere/include/exosphere/tegra.hpp b/libexosphere/include/exosphere/tegra.hpp index 370bcc3b..a6c8a0dd 100644 --- a/libexosphere/include/exosphere/tegra.hpp +++ b/libexosphere/include/exosphere/tegra.hpp @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/libexosphere/include/exosphere/tegra/tegra_clkrst.hpp b/libexosphere/include/exosphere/tegra/tegra_clkrst.hpp new file mode 100644 index 00000000..035b2859 --- /dev/null +++ b/libexosphere/include/exosphere/tegra/tegra_clkrst.hpp @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2018-2020 Atmosphère-NX + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#pragma once +#include + +/* Clock source enums. */ +#define CLK_RST_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (CLK_RST_CONTROLLER, NAME) +#define CLK_RST_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (CLK_RST_CONTROLLER, NAME, VALUE) +#define CLK_RST_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (CLK_RST_CONTROLLER, NAME, ENUM) +#define CLK_RST_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(CLK_RST_CONTROLLER, NAME, __COND__, TRUE_ENUM, FALSE_ENUM) + +#define DEFINE_CLK_RST_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (CLK_RST_CONTROLLER, NAME, __OFFSET__, __WIDTH__) +#define DEFINE_CLK_RST_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE) +#define DEFINE_CLK_RST_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE) +#define DEFINE_CLK_RST_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) +#define DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) + + +#define CLK_RST_CONTROLLER_RST_SOURCE (0x000) + +#define CLK_RST_CONTROLLER_MISC_CLK_ENB (0x048) + +#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD (0x3A4) + +DEFINE_CLK_RST_REG(MISC_CLK_ENB_CFG_ALL_VISIBLE, 28, 1); + +/* RST_DEVICES */ +#define CLK_RST_CONTROLLER_RST_DEVICES_L (0x004) +#define CLK_RST_CONTROLLER_RST_DEVICES_H (0x008) +#define CLK_RST_CONTROLLER_RST_DEVICES_U (0x00C) +#define CLK_RST_CONTROLLER_RST_DEVICES_X (0x28C) +#define CLK_RST_CONTROLLER_RST_DEVICES_Y (0x2A4) +#define CLK_RST_CONTROLLER_RST_DEVICES_V (0x358) +#define CLK_RST_CONTROLLER_RST_DEVICES_W (0x35C) + +/* CLK_OUT_ENB */ +#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L (0x010) +#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H (0x014) +#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U (0x018) +#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X (0x280) +#define CLK_RST_CONTROLLER_CLK_OUT_ENB_Y (0x298) +#define CLK_RST_CONTROLLER_CLK_OUT_ENB_V (0x360) +#define CLK_RST_CONTROLLER_CLK_OUT_ENB_W (0x364) + +/* CLK_SOURCE */ +#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA (0x178) +#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB (0x17C) +#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC (0x1A0) +#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON (0x3e8) + +/* CLK_ENB_*_INDEX */ +#define CLK_RST_CONTROLLER_CLK_ENB_UARTA_INDEX (0x06) +#define CLK_RST_CONTROLLER_CLK_ENB_UARTB_INDEX (0x07) +#define CLK_RST_CONTROLLER_CLK_ENB_UARTC_INDEX (0x17) +#define CLK_RST_CONTROLLER_CLK_ENB_ACTMON_INDEX (0x17) + +DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_ARC_CLK_OVR_ON, 19, OFF, ON); +DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_TSEC_CLK_OVR_ON, 20, OFF, ON); +DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_TSECB_CLK_OVR_ON, 21, OFF, ON); +DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_ISPB_CLK_OVR_ON, 22, OFF, ON); +DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_TZRAM_CLK_OVR_ON, 23, OFF, ON); +DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_QSPI_CLK_OVR_ON, 24, OFF, ON); +DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_A9AVP_CLK_OVR_ON, 26, OFF, ON); +DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_MPCORE_MSELECT_CLK_OVR_ON, 27, OFF, ON); +DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC1_LEGACY_TMCLK_OVR_ON, 28, OFF, ON); +DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC2_LEGACY_TMCLK_OVR_ON, 29, OFF, ON); +DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC3_LEGACY_TMCLK_OVR_ON, 30, OFF, ON); +DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC4_LEGACY_TMCLK_OVR_ON, 31, OFF, ON); + +DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTA_UARTA_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2) +DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTB_UARTB_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2) +DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTC_UARTC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2) + +DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_ACTMON_ACTMON_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, CLK_S, PLLC4_OUT1, CLK_M, PLLC4_OUT2) diff --git a/libexosphere/include/exosphere/tegra/tegra_evp.hpp b/libexosphere/include/exosphere/tegra/tegra_evp.hpp index 27d61f7c..24135720 100644 --- a/libexosphere/include/exosphere/tegra/tegra_evp.hpp +++ b/libexosphere/include/exosphere/tegra/tegra_evp.hpp @@ -16,4 +16,13 @@ #pragma once #include -#define EVP_CPU_RESET_VECTOR (0x100) +#define EVP_CPU_RESET_VECTOR (0x100) + +#define EVP_COP_RESET_VECTOR (0x200) +#define EVP_COP_UNDEF_VECTOR (0x204) +#define EVP_COP_SWI_VECTOR (0x208) +#define EVP_COP_PREFETCH_ABORT_VECTOR (0x20C) +#define EVP_COP_DATA_ABORT_VECTOR (0x210) +#define EVP_COP_RSVD_VECTOR (0x214) +#define EVP_COP_IRQ_VECTOR (0x218) +#define EVP_COP_FIQ_VECTOR (0x21C) diff --git a/libexosphere/include/exosphere/tegra/tegra_flow_ctlr.hpp b/libexosphere/include/exosphere/tegra/tegra_flow_ctlr.hpp index eca5115f..d3049333 100644 --- a/libexosphere/include/exosphere/tegra/tegra_flow_ctlr.hpp +++ b/libexosphere/include/exosphere/tegra/tegra_flow_ctlr.hpp @@ -29,6 +29,7 @@ #define FLOW_CTLR_HALT_CPU1_EVENTS (0x014) #define FLOW_CTLR_HALT_CPU2_EVENTS (0x01C) #define FLOW_CTLR_HALT_CPU3_EVENTS (0x024) +#define FLOW_CTLR_HALT_COP_EVENTS (0x004) #define FLOW_CTLR_CC4_CORE0_CTRL (0x06C) #define FLOW_CTLR_CC4_CORE1_CTRL (0x070) @@ -46,6 +47,9 @@ #define DEFINE_FLOW_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(FLOW_CTLR, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) #define DEFINE_FLOW_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (FLOW_CTLR, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) +DEFINE_FLOW_REG_BIT_ENUM(HALT_COP_EVENTS_JTAG, 28, ENABLED, DISABLED); +DEFINE_FLOW_REG_THREE_BIT_ENUM(HALT_COP_EVENTS_MODE, 29, FLOW_MODE_NONE, FLOW_MODE_RUN_AND_INT, FLOW_MODE_STOP, FLOW_MODE_STOP_AND_INT, FLOW_MODE_STOP_UNTIL_IRQ, FLOW_MODE_STOP_UNTIL_IRQ_AND_INT, FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ, RESERVED7); + DEFINE_FLOW_REG_BIT_ENUM(FLOW_DBG_QUAL_FIQ2CCPLEX_ENABLE, 28, DISABLE, ENABLE); DEFINE_FLOW_REG_BIT_ENUM(BPMP_CLUSTER_CONTROL_ACTIVE_CLUSTER, 0, FAST, SLOW); diff --git a/libexosphere/include/exosphere/tegra/tegra_mc.hpp b/libexosphere/include/exosphere/tegra/tegra_mc.hpp index b97b5c63..7f309daf 100644 --- a/libexosphere/include/exosphere/tegra/tegra_mc.hpp +++ b/libexosphere/include/exosphere/tegra/tegra_mc.hpp @@ -29,6 +29,9 @@ #define MC_SMMU_TLB_FLUSH (0x030) #define MC_SMMU_PTC_FLUSH (0x034) +#define MC_SMMU_AVPC_ASID (0x23C) +#define MC_SMMU_PPCS1_ASID (0x298) + #define MC_SECURITY_CFG0 (0x070) #define MC_SECURITY_CFG1 (0x074) #define MC_SECURITY_CFG3 (0x9BC) @@ -48,6 +51,10 @@ #define MC_SMMU_ASID_SECURITY_6 (0x9f0) #define MC_SMMU_ASID_SECURITY_7 (0x9f4) +#define MC_IRAM_BOM (0x65c) +#define MC_IRAM_TOM (0x660) +#define MC_IRAM_REG_CTRL (0x964) + #define MC_SEC_CARVEOUT_BOM (0x670) #define MC_SEC_CARVEOUT_SIZE_MB (0x674) #define MC_SEC_CARVEOUT_REG_CTRL (0x678) @@ -160,6 +167,19 @@ DEFINE_MC_REG(SMMU_PTC_CONFIG_PTC_INDEX_MAP, 0, 7); DEFINE_MC_REG(SMMU_PTC_CONFIG_PTC_REQ_LIMIT, 24, 4); DEFINE_MC_REG_BIT_ENUM(SMMU_PTC_CONFIG_PTC_CACHE_ENABLE, 29, DISABLE, ENABLE); +DEFINE_MC_REG(SMMU_PTB_ASID_CURRENT_ASID, 0, 7); + +DEFINE_MC_REG(SMMU_PTB_DATA_ASID_PDE_BASE, 0, 22); +DEFINE_MC_REG_BIT_ENUM(SMMU_PTB_DATA_ASID_NONSECURE, 29, DISABLE, ENABLE); +DEFINE_MC_REG_BIT_ENUM(SMMU_PTB_DATA_ASID_WRITABLE, 30, DISABLE, ENABLE); +DEFINE_MC_REG_BIT_ENUM(SMMU_PTB_DATA_ASID_READABLE, 31, DISABLE, ENABLE); + +DEFINE_MC_REG(SMMU_AVPC_ASID_AVPC_ASID, 0, 7); +DEFINE_MC_REG_BIT_ENUM(SMMU_AVPC_ASID_AVPC_SMMU_ENABLE, 31, DISABLE, ENABLE); + +DEFINE_MC_REG(SMMU_PPCS1_ASID_PPCS1_ASID, 0, 7); +DEFINE_MC_REG_BIT_ENUM(SMMU_PPCS1_ASID_PPCS1_SMMU_ENABLE, 31, DISABLE, ENABLE); + DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_0, 0, NONSECURE, SECURE); DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_1, 1, NONSECURE, SECURE); DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_2, 2, NONSECURE, SECURE); @@ -327,3 +347,8 @@ DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_TSECRDB, (134 - (MC_CLIENT_ACCESS_N DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_TSECWRB, (135 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE); DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_GPUSRD2, (136 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE); DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_GPUSWR2, (137 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE); + +constexpr inline u32 MC_IRAM_BOM_WRITE_MASK = 0xFFFFF000u; +constexpr inline u32 MC_IRAM_TOM_WRITE_MASK = 0xFFFFF000u; + +DEFINE_MC_REG_BIT_ENUM(IRAM_REG_CTRL_IRAM_CFG_WRITE_ACCESS, 0, ENABLED, DISABLED); diff --git a/libexosphere/source/actmon/actmon_api.cpp b/libexosphere/source/actmon/actmon_api.cpp index ee7843cb..f6c6764e 100644 --- a/libexosphere/source/actmon/actmon_api.cpp +++ b/libexosphere/source/actmon/actmon_api.cpp @@ -14,6 +14,7 @@ * along with this program. If not, see . */ #include +#include "actmon_registers.hpp" namespace ams::actmon { @@ -21,6 +22,8 @@ namespace ams::actmon { constinit uintptr_t g_register_address = secmon::MemoryRegionPhysicalDeviceActivityMonitor.GetAddress(); + constinit InterruptHandler g_interrupt_handler = nullptr; + } void SetRegisterAddress(uintptr_t address) { @@ -28,15 +31,64 @@ namespace ams::actmon { } void HandleInterrupt() { - /* TODO */ + /* Get the registers. */ + const uintptr_t ACTMON = g_register_address; + + /* Disable the actmon interrupt. */ + reg::Write(ACTMON + ACTMON_COP_CTRL, ACTMON_REG_BITS_ENUM(COP_CTRL_ENB, DISABLE)); + + /* Update the interrupt status. */ + reg::Write(ACTMON + ACTMON_COP_INTR_STATUS, reg::Read(ACTMON + ACTMON_COP_INTR_STATUS)); + + /* Invoke the handler. */ + if (g_interrupt_handler != nullptr) { + g_interrupt_handler(); + g_interrupt_handler = nullptr; + } } void StartMonitoringBpmp(InterruptHandler handler) { - /* TODO */ + /* Get the registers. */ + const uintptr_t ACTMON = g_register_address; + + /* Configure the activity monitor to poll once per microsecond. */ + reg::Write(ACTMON + ACTMON_GLB_PERIOD_CTRL, ACTMON_REG_BITS_ENUM (GLB_PERIOD_CTRL_SOURCE, USEC), + ACTMON_REG_BITS_VALUE(GLB_PERIOD_CTRL_SAMPLE_PERIOD, 0)); + + /* Configure the activity monitor to generate an interrupt the first time the event occurs. */ + reg::Write(ACTMON + ACTMON_COP_UPPER_WMARK, 0); + + /* Set the interrupt handler. */ + g_interrupt_handler = handler; + + /* Configure the activity monitor to generate events whenever the bpmp is woken up. */ + reg::Write(ACTMON + ACTMON_COP_CTRL, ACTMON_REG_BITS_ENUM (COP_CTRL_ENB, ENABLE), + ACTMON_REG_BITS_ENUM (COP_CTRL_CONSECUTIVE_ABOVE_WMARK_EN, ENABLE), + ACTMON_REG_BITS_ENUM (COP_CTRL_CONSECUTIVE_BELOW_WMARK_EN, DISABLE), + ACTMON_REG_BITS_VALUE(COP_CTRL_ABOVE_WMARK_NUM, 0), + ACTMON_REG_BITS_VALUE(COP_CTRL_BELOW_WMARK_NUM, 0), + ACTMON_REG_BITS_ENUM (COP_CTRL_WHEN_OVERFLOW_EN, DISABLE), + ACTMON_REG_BITS_ENUM (COP_CTRL_AVG_ABOVE_WMARK_EN, DISABLE), + ACTMON_REG_BITS_ENUM (COP_CTRL_AVG_BELOW_WMARK_EN, DISABLE), + ACTMON_REG_BITS_ENUM (COP_CTRL_AT_END_EN, DISABLE), + ACTMON_REG_BITS_ENUM (COP_CTRL_ENB_PERIODIC, ENABLE)); + + /* Read the activity monitor control register to make sure our configuration takes. */ + reg::Read(ACTMON + ACTMON_COP_CTRL); } void StopMonitoringBpmp() { - /* TODO */ + /* Get the registers. */ + const uintptr_t ACTMON = g_register_address; + + /* Disable the actmon interrupt. */ + reg::Write(ACTMON + ACTMON_COP_CTRL, ACTMON_REG_BITS_ENUM(COP_CTRL_ENB, DISABLE)); + + /* Update the interrupt status. */ + reg::Write(ACTMON + ACTMON_COP_INTR_STATUS, reg::Read(ACTMON + ACTMON_COP_INTR_STATUS)); + + /* Clear the interrupt handler. */ + g_interrupt_handler = nullptr; } } \ No newline at end of file diff --git a/libexosphere/source/actmon/actmon_registers.hpp b/libexosphere/source/actmon/actmon_registers.hpp new file mode 100644 index 00000000..7cfb3cdc --- /dev/null +++ b/libexosphere/source/actmon/actmon_registers.hpp @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2018-2020 Atmosphère-NX + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#include + +namespace ams::actmon { + + #define ACTMON_GLB_PERIOD_CTRL (0x004) + #define ACTMON_COP_CTRL (0x0C0) + #define ACTMON_COP_UPPER_WMARK (0x0C4) + #define ACTMON_COP_INTR_STATUS (0x0E4) + + /* Actmon source enums. */ + #define ACTMON_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (ACTMON, NAME) + #define ACTMON_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (ACTMON, NAME, VALUE) + #define ACTMON_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (ACTMON, NAME, ENUM) + #define ACTMON_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(ACTMON, NAME, __COND__, TRUE_ENUM, FALSE_ENUM) + + #define DEFINE_ACTMON_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (ACTMON, NAME, __OFFSET__, __WIDTH__) + #define DEFINE_ACTMON_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (ACTMON, NAME, __OFFSET__, ZERO, ONE) + #define DEFINE_ACTMON_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (ACTMON, NAME, __OFFSET__, ZERO, ONE, TWO, THREE) + #define DEFINE_ACTMON_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(ACTMON, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) + #define DEFINE_ACTMON_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (ACTMON, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) + + DEFINE_ACTMON_REG(GLB_PERIOD_CTRL_SAMPLE_PERIOD, 0, 8); + DEFINE_ACTMON_REG_BIT_ENUM(GLB_PERIOD_CTRL_SOURCE, 8, MSEC, USEC); + + DEFINE_ACTMON_REG(COP_CTRL_K_VAL, 10, 3); + DEFINE_ACTMON_REG_BIT_ENUM(COP_CTRL_ENB_PERIODIC, 18, DISABLE, ENABLE); + DEFINE_ACTMON_REG_BIT_ENUM(COP_CTRL_AT_END_EN, 19, DISABLE, ENABLE); + DEFINE_ACTMON_REG_BIT_ENUM(COP_CTRL_AVG_BELOW_WMARK_EN, 20, DISABLE, ENABLE); + DEFINE_ACTMON_REG_BIT_ENUM(COP_CTRL_AVG_ABOVE_WMARK_EN, 21, DISABLE, ENABLE); + DEFINE_ACTMON_REG_BIT_ENUM(COP_CTRL_WHEN_OVERFLOW_EN, 22, DISABLE, ENABLE); + DEFINE_ACTMON_REG(COP_CTRL_BELOW_WMARK_NUM, 23, 3); + DEFINE_ACTMON_REG(COP_CTRL_ABOVE_WMARK_NUM, 26, 3); + DEFINE_ACTMON_REG_BIT_ENUM(COP_CTRL_CONSECUTIVE_BELOW_WMARK_EN, 29, DISABLE, ENABLE); + DEFINE_ACTMON_REG_BIT_ENUM(COP_CTRL_CONSECUTIVE_ABOVE_WMARK_EN, 30, DISABLE, ENABLE); + DEFINE_ACTMON_REG_BIT_ENUM(COP_CTRL_ENB, 31, DISABLE, ENABLE); + +} diff --git a/libexosphere/source/clkrst/clkrst_api.cpp b/libexosphere/source/clkrst/clkrst_api.cpp index c2de3028..76601b6e 100644 --- a/libexosphere/source/clkrst/clkrst_api.cpp +++ b/libexosphere/source/clkrst/clkrst_api.cpp @@ -14,7 +14,6 @@ * along with this program. If not, see . */ #include -#include "clkrst_registers.hpp" namespace ams::clkrst { @@ -68,9 +67,10 @@ namespace ams::clkrst { .clk_div = _DIV_, \ } - DEFINE_CLOCK_PARAMETERS(UartAClock, L, UARTA, PLLP_OUT0, 0); - DEFINE_CLOCK_PARAMETERS(UartBClock, L, UARTB, PLLP_OUT0, 0); - DEFINE_CLOCK_PARAMETERS(UartCClock, H, UARTC, PLLP_OUT0, 0); + DEFINE_CLOCK_PARAMETERS(UartAClock, L, UARTA, PLLP_OUT0, 0); + DEFINE_CLOCK_PARAMETERS(UartBClock, L, UARTB, PLLP_OUT0, 0); + DEFINE_CLOCK_PARAMETERS(UartCClock, H, UARTC, PLLP_OUT0, 0); + DEFINE_CLOCK_PARAMETERS(ActmonClock, V, ACTMON, CLK_M, 0); } @@ -94,5 +94,8 @@ namespace ams::clkrst { EnableClock(UartAClock); } + void EnableActmonClock() { + EnableClock(ActmonClock); + } -} \ No newline at end of file +} diff --git a/libexosphere/source/clkrst/clkrst_registers.hpp b/libexosphere/source/clkrst/clkrst_registers.hpp deleted file mode 100644 index 5d5cd087..00000000 --- a/libexosphere/source/clkrst/clkrst_registers.hpp +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#include - -namespace ams::clkrst { - - /* Clock source enums. */ - #define CLK_RST_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (CLK_RST_CONTROLLER, NAME) - #define CLK_RST_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (CLK_RST_CONTROLLER, NAME, VALUE) - #define CLK_RST_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (CLK_RST_CONTROLLER, NAME, ENUM) - #define CLK_RST_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(CLK_RST_CONTROLLER, NAME, __COND__, TRUE_ENUM, FALSE_ENUM) - - #define DEFINE_CLK_RST_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (CLK_RST_CONTROLLER, NAME, __OFFSET__, __WIDTH__) - #define DEFINE_CLK_RST_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE) - #define DEFINE_CLK_RST_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE) - #define DEFINE_CLK_RST_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) - #define DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) - - - #define CLK_RST_CONTROLLER_RST_SOURCE (0x000) - - #define CLK_RST_CONTROLLER_MISC_CLK_ENB (0x048) - - DEFINE_CLK_RST_REG(MISC_CLK_ENB_CFG_ALL_VISIBLE, 28, 1); - - /* RST_DEVICES */ - #define CLK_RST_CONTROLLER_RST_DEVICES_L (0x004) - #define CLK_RST_CONTROLLER_RST_DEVICES_H (0x008) - #define CLK_RST_CONTROLLER_RST_DEVICES_U (0x00C) - #define CLK_RST_CONTROLLER_RST_DEVICES_X (0x28C) - #define CLK_RST_CONTROLLER_RST_DEVICES_Y (0x2A4) - #define CLK_RST_CONTROLLER_RST_DEVICES_V (0x358) - #define CLK_RST_CONTROLLER_RST_DEVICES_W (0x35C) - - /* CLK_OUT_ENB */ - #define CLK_RST_CONTROLLER_CLK_OUT_ENB_L (0x010) - #define CLK_RST_CONTROLLER_CLK_OUT_ENB_H (0x014) - #define CLK_RST_CONTROLLER_CLK_OUT_ENB_U (0x018) - #define CLK_RST_CONTROLLER_CLK_OUT_ENB_X (0x280) - #define CLK_RST_CONTROLLER_CLK_OUT_ENB_Y (0x298) - #define CLK_RST_CONTROLLER_CLK_OUT_ENB_V (0x360) - #define CLK_RST_CONTROLLER_CLK_OUT_ENB_W (0x364) - - /* CLK_SOURCE */ - #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA (0x178) - #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB (0x17C) - #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC (0x1A0) - - /* CLK_ENB_*_INDEX */ - #define CLK_RST_CONTROLLER_CLK_ENB_UARTA_INDEX (0x06) - #define CLK_RST_CONTROLLER_CLK_ENB_UARTB_INDEX (0x07) - #define CLK_RST_CONTROLLER_CLK_ENB_UARTC_INDEX (0x17) - - DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTA_UARTA_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2) - DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTB_UARTB_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2) - DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTC_UARTC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2) - -}