diff --git a/libexosphere/include/exosphere/clkrst.hpp b/libexosphere/include/exosphere/clkrst.hpp
index 2935eb2c..3299197a 100644
--- a/libexosphere/include/exosphere/clkrst.hpp
+++ b/libexosphere/include/exosphere/clkrst.hpp
@@ -29,6 +29,8 @@ namespace ams::clkrst {
     void EnableI2c1Clock();
     void EnableI2c5Clock();
 
+    void EnableCldvfsClock();
+    void EnableTzramClock();
 
     void EnableHost1xClock();
     void EnableTsecClock();
diff --git a/libexosphere/include/exosphere/pmic.hpp b/libexosphere/include/exosphere/pmic.hpp
index ea85f60a..2fc92ff7 100644
--- a/libexosphere/include/exosphere/pmic.hpp
+++ b/libexosphere/include/exosphere/pmic.hpp
@@ -36,4 +36,8 @@ namespace ams::pmic {
     bool IsAcOk();
     bool IsPowerButtonPressed();
 
+    void SetSystemSetting();
+    void EnableVddCore();
+    void EnableLdo8();
+
 }
\ No newline at end of file
diff --git a/libexosphere/source/clkrst/clkrst_api.cpp b/libexosphere/source/clkrst/clkrst_api.cpp
index b0f7f782..3227a321 100644
--- a/libexosphere/source/clkrst/clkrst_api.cpp
+++ b/libexosphere/source/clkrst/clkrst_api.cpp
@@ -88,6 +88,9 @@ namespace ams::clkrst {
         DEFINE_CLOCK_PARAMETERS(TsecClock,   U, TSEC,   PLLP_OUT0, 2);
         DEFINE_CLOCK_PARAMETERS(Sor1Clock,   X, SOR1,   PLLP_OUT0, 2);
 
+        DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(CldvfsClock, W, DVFS);
+        DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(TzramClock,  V, TZRAM);
+
         DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(SorSafeClock, Y, SOR_SAFE);
         DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(Sor0Clock,    X, SOR0);
         DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(KfuseClock,   H, KFUSE);
@@ -126,6 +129,14 @@ namespace ams::clkrst {
         EnableClock(I2c5Clock);
     }
 
+    void EnableCldvfsClock() {
+        EnableClock(CldvfsClock);
+    }
+
+    void EnableTzramClock() {
+        EnableClock(TzramClock);
+    }
+
     void EnableHost1xClock() {
         EnableClock(Host1xClock);
     }
diff --git a/libexosphere/source/pmic/pmic_api.cpp b/libexosphere/source/pmic/pmic_api.cpp
index 76ee8c68..84c8fbf6 100644
--- a/libexosphere/source/pmic/pmic_api.cpp
+++ b/libexosphere/source/pmic/pmic_api.cpp
@@ -215,4 +215,15 @@ namespace ams::pmic {
         return (GetPmicOnOffStat() & (1 << 2)) != 0;
     }
 
+    void SetSystemSetting() {
+        /* TODO */
+    }
+    void EnableVddCore() {
+        /* TODO */
+    }
+
+    void EnableLdo8() {
+        /* TODO */
+    }
+
 }
diff --git a/libvapours/include/vapours/tegra/tegra_clkrst.hpp b/libvapours/include/vapours/tegra/tegra_clkrst.hpp
index 8287db38..7f5fc29d 100644
--- a/libvapours/include/vapours/tegra/tegra_clkrst.hpp
+++ b/libvapours/include/vapours/tegra/tegra_clkrst.hpp
@@ -36,6 +36,7 @@
 
 #define CLK_RST_CONTROLLER_RST_SOURCE            (0x000)
 
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY     (0x028)
 #define CLK_RST_CONTROLLER_MISC_CLK_ENB          (0x048)
 #define CLK_RST_CONTROLLER_OSC_CTRL              (0x050)
 #define CLK_RST_CONTROLLER_PLLD_BASE             (0x0D0)
@@ -57,6 +58,11 @@
 #define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD (0x3A4)
 #define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE (0x554)
 
+DEFINE_CLK_RST_REG_THREE_BIT_ENUM(SCLK_BURST_POLICY_SWAKEUP_IDLE_SOURCE,  0, CLKM, PLLC_OUT1, PLLC4_OUT3PLLP_OUT4, PLLP_OUT0, PLLP_OUT2, PLLC4_OUT1PLLC_OUT0, CLK_SCLKS, PLLC4_OUT2);
+DEFINE_CLK_RST_REG_THREE_BIT_ENUM(SCLK_BURST_POLICY_SWAKEUP_RUN_SOURCE,   4, CLKM, PLLC_OUT1, PLLC4_OUT3PLLP_OUT4, PLLP_OUT0, PLLP_OUT2, PLLC4_OUT1PLLC_OUT0, CLK_SCLKS, PLLC4_OUT2);
+DEFINE_CLK_RST_REG_THREE_BIT_ENUM(SCLK_BURST_POLICY_SWAKEUP_IRQ_SOURCE,   8, CLKM, PLLC_OUT1, PLLC4_OUT3PLLP_OUT4, PLLP_OUT0, PLLP_OUT2, PLLC4_OUT1PLLC_OUT0, CLK_SCLKS, PLLC4_OUT2);
+DEFINE_CLK_RST_REG_THREE_BIT_ENUM(SCLK_BURST_POLICY_SWAKEUP_FIQ_SOURCE,  12, CLKM, PLLC_OUT1, PLLC4_OUT3PLLP_OUT4, PLLP_OUT0, PLLP_OUT2, PLLC4_OUT1PLLC_OUT0, CLK_SCLKS, PLLC4_OUT2);
+
 DEFINE_CLK_RST_REG(MISC_CLK_ENB_CFG_ALL_VISIBLE, 28, 1);
 
 DEFINE_CLK_RST_REG_BIT_ENUM(OSC_CTRL_XOE, 0, DISABLE, ENABLE);
@@ -209,6 +215,10 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLC4_BASE_PLLC4_ENABLE, 30, DISABLE, ENABLE);
 
 #define CLK_RST_CONTROLLER_CLK_ENB_ACTMON_INDEX (0x17)
 
+#define CLK_RST_CONTROLLER_CLK_ENB_DVFS_INDEX (0x1B)
+
+#define CLK_RST_CONTROLLER_CLK_ENB_TZRAM_INDEX (0x1E)
+
 #define CLK_RST_CONTROLLER_CLK_ENB_HOST1X_INDEX   (0x1C)
 #define CLK_RST_CONTROLLER_CLK_ENB_TSEC_INDEX     (0x13)
 #define CLK_RST_CONTROLLER_CLK_ENB_SOR0_INDEX     (0x16)