exo2: suspend fixes (sleep/wake now works on hardware)

This commit is contained in:
Michael Scire 2020-06-08 03:53:40 -07:00
parent 4ba07f80f8
commit 43569123cd
4 changed files with 15 additions and 3 deletions

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@ -63,6 +63,9 @@ DEFINE_CLK_RST_REG(MISC_CLK_ENB_CFG_ALL_VISIBLE, 28, 1);
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC (0x1A0) #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC (0x1A0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON (0x3E8) #define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON (0x3E8)
/* RST_DEV_*_SET */
#define CLK_RST_CONTROLLER_RST_DEV_L_SET (0x300)
/* RST_DEV_*_CLR */ /* RST_DEV_*_CLR */
#define CLK_RST_CONTROLLER_RST_DEV_L_CLR (0x304) #define CLK_RST_CONTROLLER_RST_DEV_L_CLR (0x304)
@ -100,4 +103,6 @@ DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTC_UARTC_CLK_SRC, 29, PLLP_OUT0,
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_ACTMON_ACTMON_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, CLK_S, PLLC4_OUT1, CLK_M, PLLC4_OUT2); DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_ACTMON_ACTMON_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, CLK_S, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_L_SET_SET_COP_RST, 1, DISABLE, ENABLE);
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_L_CLR_CLR_COP_RST, 1, DISABLE, ENABLE); DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_L_CLR_CLR_COP_RST, 1, DISABLE, ENABLE);

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@ -42,6 +42,8 @@
#define APBDEV_PMC_WAKE_DELAY (0x0E0) #define APBDEV_PMC_WAKE_DELAY (0x0E0)
#define APBDEV_PMC_PWR_DET_VAL (0x0E4) #define APBDEV_PMC_PWR_DET_VAL (0x0E4)
#define APBDEV_PMC_CRYPTO_OP (0x0F4) #define APBDEV_PMC_CRYPTO_OP (0x0F4)
#define APBDEV_PMC_SCRATCH31 (0x118)
#define APBDEV_PMC_SCRATCH32 (0x11C)
#define APBDEV_PMC_WAKE2_MASK (0x160) #define APBDEV_PMC_WAKE2_MASK (0x160)
#define APBDEV_PMC_WAKE2_LVL (0x164) #define APBDEV_PMC_WAKE2_LVL (0x164)
#define APBDEV_PMC_WAKE2_STATUS (0x168) #define APBDEV_PMC_WAKE2_STATUS (0x168)

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@ -21,6 +21,7 @@ namespace ams::log {
constexpr inline uart::Port UartLogPort = uart::Port_ReservedDebug; constexpr inline uart::Port UartLogPort = uart::Port_ReservedDebug;
constinit bool g_initialized_uart = false; constinit bool g_initialized_uart = false;
constinit bool g_logging_enabled = false;
constexpr inline u32 UartPortFlags = [] { constexpr inline u32 UartPortFlags = [] {
if constexpr (UartLogPort == uart::Port_ReservedDebug) { if constexpr (UartLogPort == uart::Port_ReservedDebug) {
@ -75,14 +76,18 @@ namespace ams::log {
g_initialized_uart = false; g_initialized_uart = false;
} }
void SetDebugLogEnabled(bool en) {
g_logging_enabled = en;
}
void SendText(const void *text, size_t size) { void SendText(const void *text, size_t size) {
if (g_initialized_uart) { if (g_initialized_uart && g_logging_enabled) {
uart::SendText(UartLogPort, text, size); uart::SendText(UartLogPort, text, size);
} }
} }
void Flush() { void Flush() {
if (g_initialized_uart) { if (g_initialized_uart && g_logging_enabled) {
uart::WaitFlush(UartLogPort); uart::WaitFlush(UartLogPort);
} }
} }

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@ -44,7 +44,7 @@ namespace ams::se {
} }
/* Execute the operation. */ /* Execute the operation. */
ExecuteOperation(SE, SE_OPERATION_OP_CTX_SAVE, dst, dst_size, src, src_size); ExecuteOperation(SE, SE_OPERATION_OP_CTX_SAVE, temp, dst_size, src, src_size);
/* Copy output from the operation, if any. */ /* Copy output from the operation, if any. */
if (dst_size > 0) { if (dst_size > 0) {