diff --git a/libvapours/include/vapours/tegra.hpp b/libvapours/include/vapours/tegra.hpp index 52a04cbb..ac69ce1b 100644 --- a/libvapours/include/vapours/tegra.hpp +++ b/libvapours/include/vapours/tegra.hpp @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include diff --git a/libvapours/include/vapours/tegra/tegra_apb_misc.hpp b/libvapours/include/vapours/tegra/tegra_apb_misc.hpp index 1ceabe5b..47fa9bcc 100644 --- a/libvapours/include/vapours/tegra/tegra_apb_misc.hpp +++ b/libvapours/include/vapours/tegra/tegra_apb_misc.hpp @@ -33,6 +33,9 @@ #define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL (0xAB4) #define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL (0xABC) +/* Mariko only */ +#define APB_MISC_GP_DSI_PAD_CONTROL (0xAC0) + #define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 (0xc00) #define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 (0xc00) #define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 (0xc04) diff --git a/libvapours/include/vapours/tegra/tegra_clkrst.hpp b/libvapours/include/vapours/tegra/tegra_clkrst.hpp index 1be60be6..21200036 100644 --- a/libvapours/include/vapours/tegra/tegra_clkrst.hpp +++ b/libvapours/include/vapours/tegra/tegra_clkrst.hpp @@ -240,12 +240,18 @@ DEFINE_CLK_RST_REG(CLK_SOURCE_MSELECT_MSELECT_CLK_DIVISOR, 0, 8); DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_ACTMON_ACTMON_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, CLK_S, PLLC4_OUT1, CLK_M, PLLC4_OUT2); +DEFINE_CLK_RST_REG(CLK_SOURCE_DSIA_LP_DSIA_LP_CLK_DIVISOR, 0, 8); +DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_DSIA_LP_DSIA_LP_CLK_SRC, 29, PLLP_OUT0, RSVD1, PLLC_OUT0, PLLC4_OUT0, PLLC4_OUT1, PLLC4_OUT2, CLK_M, RSVD7); + DEFINE_CLK_RST_REG(CLK_SOURCE_DVFS_REF_DVFS_REF_DIVISOR, 0, 8); DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_DVFS_REF_DVFS_REF_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2); DEFINE_CLK_RST_REG(CLK_SOURCE_DVFS_SOC_DVFS_SOC_DIVISOR, 0, 8); DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_DVFS_SOC_DVFS_SOC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2); +DEFINE_CLK_RST_REG(CLK_SOURCE_UART_FST_MIPI_CAL_UART_FST_MIPI_CAL_CLK_DIVISOR, 0, 8); +DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UART_FST_MIPI_CAL_UART_FST_MIPI_CAL_CLK_SRC, 29, PLLP_OUT3, PLLC_OUT0, PLLC2_OUT0_2, RSVD3, PLLC2_OUT0_4, RSVD5, CLK_M, RSVD7); + DEFINE_CLK_RST_REG(CLK_SOURCE_LEGACY_TM_CLK_DIVISOR, 0, 8); DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_LEGACY_TM_CLK_SRC, 29, PLLP_OUT3, PLLC_OUT0, PLLC2_OUT0, CLK_M, PLLP_OUT0, PLLC4_OUT0, PLLC4_OUT1, PLLC4_OUT2); @@ -264,59 +270,65 @@ DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET3, 19, DISABLE, ENA DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_NONCPURESET, 29, DISABLE, ENABLE); /* TODO: Actually include all devices. */ -#define CLK_RST_FOREACH_DEVICE(HANDLER) \ - HANDLER(L, CPU, 0, 0) \ - HANDLER(L, RTC, 0, 4) \ - HANDLER(L, TMR, 0, 5) \ - HANDLER(L, GPIO, 0, 8) \ - HANDLER(L, SDMMC2, 0, 9) \ - HANDLER(L, SDMMC1, 0, 14) \ - HANDLER(L, SDMMC4, 0, 15) \ - HANDLER(L, USBD, 0, 22) \ - HANDLER(L, CACHE2, 0, 31) \ - HANDLER(H, MEM, 1, 0) \ - HANDLER(H, AHBDMA, 1, 1) \ - HANDLER(H, APBDMA, 1, 2) \ - HANDLER(H, PMC, 1, 6) \ - HANDLER(H, FUSE, 1, 7) \ - HANDLER(H, KFUSE, 1, 8) \ - HANDLER(H, I2C5, 1, 15) \ - HANDLER(H, EMC, 1, 25) \ - HANDLER(H, USB2, 1, 26) \ - HANDLER(U, SDMMC3, 2, 5) \ - HANDLER(U, CSITE, 2, 9) \ - HANDLER(U, IRAMA, 2, 20) \ - HANDLER(U, IRAMB, 2, 21) \ - HANDLER(U, IRAMC, 2, 22) \ - HANDLER(U, IRAMD, 2, 23) \ - HANDLER(U, CRAM2, 2, 24) \ - HANDLER(V, CPUG, 3, 0) \ - HANDLER(V, MSELECT, 3, 3) \ - HANDLER(V, SPDIF_DOUBLER, 3, 22) \ - HANDLER(V, ACTMON, 3, 23) \ - HANDLER(V, TZRAM, 3, 30) \ - HANDLER(V, SE, 3, 31) \ - HANDLER(W, PCIERX0, 4, 2) \ - HANDLER(W, PCIERX1, 4, 3) \ - HANDLER(W, PCIERX2, 4, 4) \ - HANDLER(W, PCIERX3, 4, 5) \ - HANDLER(W, PCIERX4, 4, 6) \ - HANDLER(W, PCIERX5, 4, 7) \ - HANDLER(W, ENTROPY, 4, 21) \ - HANDLER(W, DVFS, 4, 27) \ - HANDLER(W, MC1, 4, 30) \ - HANDLER(X, MC_CAPA, 5, 7) \ - HANDLER(X, MC_CBPA, 5, 8) \ - HANDLER(X, MC_CPU, 5, 9) \ - HANDLER(X, MC_BBC, 5, 10) \ - HANDLER(X, EMC_DLL, 5, 14) \ - HANDLER(X, GPU, 5, 24) \ - HANDLER(X, DBGAPB, 5, 25) \ - HANDLER(X, PLLG_REF, 5, 29) \ - HANDLER(Y, LEGACY_TM, 6, 1) \ - HANDLER(Y, MC_CCPA, 6, 8) \ - HANDLER(Y, MC_CDPA, 6, 9) \ - HANDLER(Y, PLLP_OUT_CPU, 6, 31) +#define CLK_RST_FOREACH_DEVICE(HANDLER) \ + HANDLER(L, CPU, 0, 0) \ + HANDLER(L, RTC, 0, 4) \ + HANDLER(L, TMR, 0, 5) \ + HANDLER(L, GPIO, 0, 8) \ + HANDLER(L, SDMMC2, 0, 9) \ + HANDLER(L, SDMMC1, 0, 14) \ + HANDLER(L, SDMMC4, 0, 15) \ + HANDLER(L, USBD, 0, 22) \ + HANDLER(L, DISP1, 0, 27) \ + HANDLER(L, HOST1X, 0, 28) \ + HANDLER(L, CACHE2, 0, 31) \ + HANDLER(H, MEM, 1, 0) \ + HANDLER(H, AHBDMA, 1, 1) \ + HANDLER(H, APBDMA, 1, 2) \ + HANDLER(H, PMC, 1, 6) \ + HANDLER(H, FUSE, 1, 7) \ + HANDLER(H, KFUSE, 1, 8) \ + HANDLER(H, I2C5, 1, 15) \ + HANDLER(H, DSI, 1, 16) \ + HANDLER(H, MIPI_CAL, 1, 24) \ + HANDLER(H, EMC, 1, 25) \ + HANDLER(H, USB2, 1, 26) \ + HANDLER(U, SDMMC3, 2, 5) \ + HANDLER(U, CSITE, 2, 9) \ + HANDLER(U, IRAMA, 2, 20) \ + HANDLER(U, IRAMB, 2, 21) \ + HANDLER(U, IRAMC, 2, 22) \ + HANDLER(U, IRAMD, 2, 23) \ + HANDLER(U, CRAM2, 2, 24) \ + HANDLER(V, CPUG, 3, 0) \ + HANDLER(V, MSELECT, 3, 3) \ + HANDLER(V, SPDIF_DOUBLER, 3, 22) \ + HANDLER(V, ACTMON, 3, 23) \ + HANDLER(V, TZRAM, 3, 30) \ + HANDLER(V, SE, 3, 31) \ + HANDLER(W, PCIERX0, 4, 2) \ + HANDLER(W, PCIERX1, 4, 3) \ + HANDLER(W, PCIERX2, 4, 4) \ + HANDLER(W, PCIERX3, 4, 5) \ + HANDLER(W, PCIERX4, 4, 6) \ + HANDLER(W, PCIERX5, 4, 7) \ + HANDLER(W, DSIA_LP, 4, 19) \ + HANDLER(W, ENTROPY, 4, 21) \ + HANDLER(W, DVFS, 4, 27) \ + HANDLER(W, MC1, 4, 30) \ + HANDLER(X, MC_CAPA, 5, 7) \ + HANDLER(X, MC_CBPA, 5, 8) \ + HANDLER(X, MC_CPU, 5, 9) \ + HANDLER(X, MC_BBC, 5, 10) \ + HANDLER(X, EMC_DLL, 5, 14) \ + HANDLER(X, UART_FST_MIPI_CAL, 5, 17) \ + HANDLER(X, GPU, 5, 24) \ + HANDLER(X, DBGAPB, 5, 25) \ + HANDLER(X, PLLG_REF, 5, 29) \ + HANDLER(Y, LEGACY_TM, 6, 1) \ + HANDLER(Y, MC_CCPA, 6, 8) \ + HANDLER(Y, MC_CDPA, 6, 9) \ + HANDLER(Y, PLLP_OUT_CPU, 6, 31) #define CLK_RST_DEFINE_SET_CLR_REG(REGISTER, DEVICE, REGISTER_INDEX, DEVICE_INDEX) \ DEFINE_CLK_RST_REG_BIT_ENUM(CLK_ENB_##REGISTER##_SET_SET_CLK_ENB_##DEVICE, DEVICE_INDEX, DISABLE, ENABLE); \ diff --git a/libvapours/include/vapours/tegra/tegra_mipi_cal.hpp b/libvapours/include/vapours/tegra/tegra_mipi_cal.hpp new file mode 100644 index 00000000..efff2ed9 --- /dev/null +++ b/libvapours/include/vapours/tegra/tegra_mipi_cal.hpp @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2018-2020 Atmosphère-NX + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#pragma once +#include +#include +#include +#include +#include +#include + +#define MIPI_CAL_MIPI_CAL_CTRL (0x000) +#define MIPI_CAL_CIL_MIPI_CAL_STATUS (0x008) +#define MIPI_CAL_CILA_MIPI_CAL_CONFIG (0x014) +#define MIPI_CAL_CILB_MIPI_CAL_CONFIG (0x018) +#define MIPI_CAL_CILC_MIPI_CAL_CONFIG (0x01C) +#define MIPI_CAL_CILD_MIPI_CAL_CONFIG (0x020) +#define MIPI_CAL_CILE_MIPI_CAL_CONFIG (0x024) +#define MIPI_CAL_CILF_MIPI_CAL_CONFIG (0x028) +#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG (0x038) +#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG (0x03C) +#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG (0x040) +#define MIPI_CAL_DSID_MIPI_CAL_CONFIG (0x044) +#define MIPI_CAL_MIPI_BIAS_PAD_CFG0 (0x058) +#define MIPI_CAL_MIPI_BIAS_PAD_CFG1 (0x05C) +#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 (0x060) +#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2 (0x064) +#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 (0x068) +#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2 (0x070) +#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 (0x074) + +#define MIPI_CAL_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (MIPI_CAL, NAME) +#define MIPI_CAL_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (MIPI_CAL, NAME, VALUE) +#define MIPI_CAL_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (MIPI_CAL, NAME, ENUM) +#define MIPI_CAL_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(MIPI_CAL, NAME, __COND__, TRUE_ENUM, FALSE_ENUM) + +#define DEFINE_MIPI_CAL_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (MIPI_CAL, NAME, __OFFSET__, __WIDTH__) +#define DEFINE_MIPI_CAL_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (MIPI_CAL, NAME, __OFFSET__, ZERO, ONE) +#define DEFINE_MIPI_CAL_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (MIPI_CAL, NAME, __OFFSET__, ZERO, ONE, TWO, THREE) +#define DEFINE_MIPI_CAL_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(MIPI_CAL, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) +#define DEFINE_MIPI_CAL_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (MIPI_CAL, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) diff --git a/libvapours/include/vapours/tegra/tegra_pmc.hpp b/libvapours/include/vapours/tegra/tegra_pmc.hpp index e518c668..17a35201 100644 --- a/libvapours/include/vapours/tegra/tegra_pmc.hpp +++ b/libvapours/include/vapours/tegra/tegra_pmc.hpp @@ -210,7 +210,8 @@ DEFINE_PMC_REG_BIT_ENUM(PWR_DET_VAL_SDMMC1, 12, DISABLE, ENABLE); DEFINE_PMC_REG(SET_SW_CLAMP_CRAIL, 0, 1); -DEFINE_PMC_REG_TWO_BIT_ENUM(IO_DPD_REQ_CODE, 30, IDLE, DPD_OFF, DPD_ON, RESERVED3); +DEFINE_PMC_REG_TWO_BIT_ENUM(IO_DPD_REQ_CODE, 30, IDLE, DPD_OFF, DPD_ON, RESERVED3); +DEFINE_PMC_REG_TWO_BIT_ENUM(IO_DPD2_REQ_CODE, 30, IDLE, DPD_OFF, DPD_ON, RESERVED3); DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CRAIL, 0, DISABLE, ENABLE); DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_TE, 1, DISABLE, ENABLE);