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fusee_cpp: add logic for loading mtc overlays

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This commit is contained in:
Michael Scire 2021-08-23 21:15:51 -07:00
parent 797c61b066
commit 4043c52691
1 changed files with 5 additions and 1 deletions
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6
libexosphere/source/clkrst/clkrst_api.cpp
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@ -153,7 +153,6 @@ namespace ams::clkrst {
reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_ENUM(PLLC_BASE_PLLC_ENABLE, DISABLE)); reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_ENUM(PLLC_BASE_PLLC_ENABLE, DISABLE));
reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_ENUM(PLLC_BASE_PLLC_REF_DIS, REF_DISABLE)); reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_ENUM(PLLC_BASE_PLLC_REF_DIS, REF_DISABLE));
reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_ENUM(PLLC_BASE_PLLC_REF_DIS, REF_DISABLE));
reg::SetBits(g_register_address + CLK_RST_CONTROLLER_PLLC_MISC1, (1u << 27)); reg::SetBits(g_register_address + CLK_RST_CONTROLLER_PLLC_MISC1, (1u << 27));
reg::SetBits(g_register_address + CLK_RST_CONTROLLER_PLLC_MISC, (1u << 30)); reg::SetBits(g_register_address + CLK_RST_CONTROLLER_PLLC_MISC, (1u << 30));
util::WaitMicroSeconds(10); util::WaitMicroSeconds(10);
@ -281,6 +280,11 @@ namespace ams::clkrst {
rate = BpmpClockRate_589MHz; rate = BpmpClockRate_589MHz;
} }
/* Change the rate, if we need to. */
if (rate == prev_rate) {
return prev_rate;
}
/* Configure the rate. */ /* Configure the rate. */
if (rate != BpmpClockRate_408MHz) { if (rate != BpmpClockRate_408MHz) {
/* If we were previously overclocked, restore to PLLP_OUT. */ /* If we were previously overclocked, restore to PLLP_OUT. */