diff --git a/libexosphere/include/exosphere/reg.hpp b/libexosphere/include/exosphere/reg.hpp
index a16d6619..aa0de083 100644
--- a/libexosphere/include/exosphere/reg.hpp
+++ b/libexosphere/include/exosphere/reg.hpp
@@ -18,14 +18,18 @@
 
 namespace ams::reg {
 
-    using BitsValue = std::tuple<u32, u32, u32>;
-    using BitsMask  = std::tuple<u32, u32>;
+    using BitsValue = std::tuple<u16, u16, u32>;
+    using BitsMask  = std::tuple<u16, u16>;
 
-    constexpr ALWAYS_INLINE u32 GetOffset(const BitsMask v)  { return std::get<0>(v); }
-    constexpr ALWAYS_INLINE u32 GetOffset(const BitsValue v) { return std::get<0>(v); }
-    constexpr ALWAYS_INLINE u32 GetWidth(const BitsMask v)   { return std::get<1>(v); }
-    constexpr ALWAYS_INLINE u32 GetWidth(const BitsValue v)  { return std::get<1>(v); }
-    constexpr ALWAYS_INLINE u32 GetValue(const BitsValue v)  { return std::get<2>(v); }
+    constexpr ALWAYS_INLINE u32 GetOffset(const BitsMask v)  { return static_cast<u32>(std::get<0>(v)); }
+    constexpr ALWAYS_INLINE u32 GetOffset(const BitsValue v) { return static_cast<u32>(std::get<0>(v)); }
+    constexpr ALWAYS_INLINE u32 GetWidth(const BitsMask v)   { return static_cast<u32>(std::get<1>(v)); }
+    constexpr ALWAYS_INLINE u32 GetWidth(const BitsValue v)  { return static_cast<u32>(std::get<1>(v)); }
+    constexpr ALWAYS_INLINE u32 GetValue(const BitsValue v)  { return static_cast<u32>(std::get<2>(v)); }
+
+    constexpr ALWAYS_INLINE ::ams::reg::BitsValue GetValue(const BitsMask m, const u32 v) {
+        return ::ams::reg::BitsValue{GetOffset(m), GetWidth(m), v};
+    }
 
     constexpr ALWAYS_INLINE u32 EncodeMask(const BitsMask v) {
         return (~0u >> (BITSIZEOF(u32) - GetWidth(v))) << GetOffset(v);
@@ -138,6 +142,8 @@ namespace ams::reg {
     #define REG_BITS_MASK(OFFSET, WIDTH)         ::ams::reg::BitsMask{OFFSET, WIDTH}
     #define REG_BITS_VALUE(OFFSET, WIDTH, VALUE) ::ams::reg::BitsValue{OFFSET, WIDTH, VALUE}
 
+    #define REG_BITS_VALUE_FROM_MASK(MASK, VALUE) ::ams::reg::GetValue(MASK, VALUE)
+
     #define REG_NAMED_BITS_MASK(PREFIX, NAME)         REG_BITS_MASK(PREFIX##_##NAME##_OFFSET, PREFIX##_##NAME##_WIDTH)
     #define REG_NAMED_BITS_VALUE(PREFIX, NAME, VALUE) REG_BITS_VALUE(PREFIX##_##NAME##_OFFSET, PREFIX##_##NAME##_WIDTH, VALUE)
     #define REG_NAMED_BITS_ENUM(PREFIX, NAME, ENUM)   REG_BITS_VALUE(PREFIX##_##NAME##_OFFSET, PREFIX##_##NAME##_WIDTH, PREFIX##_##NAME##_##ENUM)
diff --git a/libexosphere/include/exosphere/tegra/tegra_clkrst.hpp b/libexosphere/include/exosphere/tegra/tegra_clkrst.hpp
index 1529b566..3659194a 100644
--- a/libexosphere/include/exosphere/tegra/tegra_clkrst.hpp
+++ b/libexosphere/include/exosphere/tegra/tegra_clkrst.hpp
@@ -71,6 +71,10 @@ DEFINE_CLK_RST_REG(MISC_CLK_ENB_CFG_ALL_VISIBLE, 28, 1);
 #define CLK_RST_CONTROLLER_CLK_ENB_UARTC_INDEX  (0x17)
 #define CLK_RST_CONTROLLER_CLK_ENB_ACTMON_INDEX (0x17)
 
+/* RST_CPUG_CMPLX_* */
+#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET   (0x450)
+#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR   (0x454)
+
 DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_ARC_CLK_OVR_ON,             19, OFF, ON);
 DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_TSEC_CLK_OVR_ON,            20, OFF, ON);
 DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_TSECB_CLK_OVR_ON,           21, OFF, ON);
diff --git a/libexosphere/include/exosphere/tegra/tegra_pmc.hpp b/libexosphere/include/exosphere/tegra/tegra_pmc.hpp
index ee10391f..27a80956 100644
--- a/libexosphere/include/exosphere/tegra/tegra_pmc.hpp
+++ b/libexosphere/include/exosphere/tegra/tegra_pmc.hpp
@@ -103,6 +103,41 @@ DEFINE_PMC_REG_BIT_ENUM(DPD_SAMPLE_ON, 0, DISABLE, ENABLE);
 DEFINE_PMC_REG_BIT_ENUM(DPD_ENABLE_ON,          0, DISABLE, ENABLE);
 DEFINE_PMC_REG_BIT_ENUM(DPD_ENABLE_TSC_MULT_EN, 1, DISABLE, ENABLE);
 
+DEFINE_PMC_REG_BIT_ENUM(PWRGATE_TOGGLE_START, 8, DISABLE, ENABLE);
+
+DEFINE_PMC_REG(PWRGATE_TOGGLE_PARTID, 0, 5);
+
+enum APBDEV_PMC_PWRGATE_TOGGLE_PARTID : u8 {
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CRAIL  =  0,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_VE     =  2,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_PCX    =  3,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_MPE    =  6,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_SAX    =  8,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE1    =  9,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE2    = 10,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE3    = 11,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE0    = 14,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_C0NC   = 15,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_SOR    = 17,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_DIS    = 18,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_DISB   = 19,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_XUSBA  = 20,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_XUSBB  = 21,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_XUSBC  = 22,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_VIC    = 23,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_IRAM   = 24,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_NVDEC  = 25,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_NVJPG  = 26,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_AUD    = 27,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_DFD    = 28,
+    APBDEV_PMC_PWRGATE_TOGGLE_PARTID_VE2    = 29,
+};
+
+enum APBDEV_PMC_PWRGATE_STATUS_STATUS {
+    APBDEV_PMC_PWRGATE_STATUS_STATUS_OFF = 0,
+    APBDEV_PMC_PWRGATE_STATUS_STATUS_ON  = 1,
+};
+
 DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_CRAIL,  0, OFF, ON);
 DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_VE,     2, OFF, ON);
 DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_PCX,    3, OFF, ON);